Using the MSI state transition of a block for cache coherency of two cores that are sharing memory but have their own L1 cache fill in the table below: SNOOP RD,WR ON BUS LOCAL READ PUT RD ON BUS LOCAL READ INVALID V=0 SHARED V=1 D=0 SNOOP WR ON BUS SNOOP RD ON BUS LOCAL WRITE PUT WR ON BUS SNOOP WR ON BUS WRITE BACK MODIFIED V=0 D=1 SNOOP RD ON BUS WRITE BACK LOCAL WRITE PUT INVALIDATION ON BUS LOCAL READ LOCAL WRITE C1 C2 C3 State of C1 L1 State of C2 L1 Read X Read X Write X Write X
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Initially, both C1 and C2 are in the Invalid state (I), as they have not yet accessed the block. Show more…
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