Using Verilog:
I have some starter code for a module that works. I want to split it up into three modules and instantiate.
Starter code:
// Verilog behavioral model of a four-phase clock
module FourPhaseClockVerilog (input Clock, Clear,
// name the module
// declare inputs
output reg [0:3] P);
// declare outputs as a register for convenience
reg [1:0] state, nextstate; // declare internal state and next state variables
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10; // parameterize states
always @(posedge Clock, negedge Clear)
// watch for changes of Clock or Clear
if (Clear == 0) state <= S0; // active-low Clear takes the machine to so else state <= nextstate; // state change occurs on positive edge of Clock
always @(state)
// derive output and next state after each state change
case (state)
// case statement specifies output and next state for each state
S0: begin P = 4'b1000; nextstate = S1; end
S1: begin P = 4'b0100; nextstate = S2; end
S2: begin P = 4'b0010; nextstate = S3; end
S3: begin P = 4'b0001; nextstate = S0; end
endcase
endmodule