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Problem 1 (30 points) Consider a word addressing architecture with 12-bit memory addresses. (1) Which bits of the address would be used in the tag, index and offset in a direct- mapped cache with 64 1-word blocks? (2) Which bits of the address would be used in the tag, index and offset in a direct- mapped cache with 32 2-word blocks? (3) Which bits of the address would be used in the tag, index and offset in a direct- mapped cache with 16 4-word blocks? 1 (4) We now double the total capacity of the memory and make it 2-way set associative with 64 sets with two 1-word entries each. Which bits of the address would be used in the tag, index and offset? Compare this with the first question above. (5) Doubling the total capacity of the memory one more time makes it 4-way set asso- ciative with 64 sets with four 1-word entries each. Which bits of the address would be used in the tag, index and offset?

Name: problem 1 30 points consider a word addressing architecture with 12 bit memory addresses 1 which bits of the address would be used in the tag index and offset in a direct mapped cache with 6 44231
Uploaded: 2023-06-24T01:36:05-08:00
Channel: Akash M
Description: problem 1 30 points consider a word addressing architecture with 12 bit memory addresses 1 which bits of the address would be used in the tag index and offset in a direct mapped cache with 6 44231

          Problem 1 (30 points) Consider a word addressing architecture with 12-bit memory
addresses.
(1) Which bits of the address would be used in the tag, index and offset in a direct-
mapped cache with 64 1-word blocks?
(2) Which bits of the address would be used in the tag, index and offset in a direct-
mapped cache with 32 2-word blocks?
(3) Which bits of the address would be used in the tag, index and offset in a direct-
mapped cache with 16 4-word blocks?
1
(4) We now double the total capacity of the memory and make it 2-way set associative
with 64 sets with two 1-word entries each. Which bits of the address would be used
in the tag, index and offset? Compare this with the first question above.
(5) Doubling the total capacity of the memory one more time makes it 4-way set asso-
ciative with 64 sets with four 1-word entries each. Which bits of the address would
be used in the tag, index and offset?

Added by Corey M.

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