Write VHDL code (entity and architecture) for following State Machine. Using waveform show that state transitions and outputs are correct.
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The given state machine has the following inputs and outputs: - Inputs: clk (clock signal), RESET (reset signal), X (input signal) - Outputs: So (output signal) Show more…
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Design a 4-bit shift register with the following specifications: - An asynchronous active-low clear (ClrN) - A rising-edge triggered clock (CLK) - An active-high load signal (Ld) with parallel data input (D) - A function select signal (S) - When S = 0, the register shifts right with a serial data input (SI) - When S = 1, the register shifts right with sign extension (copy the sign bit) a) Draw the logic symbol and a truth table for the 4-bit shift register. b) Write a complete VHDL model (entity and behavioral architecture) for the 4-bit shift register. c) Write a VHDL testbench for the 4-bit shift register. Simulate the shift register for the following test sequence: - Load 0011 - Shift right 3 times with S = 0 and SI = 1 - Shift right 2 times with S = 0 and SI = 0 - Clear - Load 1100 - Shift right 2 times with S = 1 and SI = 0
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In the following VHDL process A, B, C, and D are all integers that have a value of 0 at time = 10 ns. If E changes from '0' to '1' at time 20 ns, specify the time at which each signal will change and the value to which it will change. p1: process wait on E; A <= 1 after 15 ns; B <= A + 1; C <= B + 1 after 10 ns; D <= B + 2 after 3 ns; A <= A + 5 after 15 ns; B <= B + 7; end process p1;
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