As a means of enhancing heat transfer from highperformance logic chips, it is common to attach a heat $\sin k$ to the chip surface in order to increase the surface area available for convection heat transfer. Because of the ease with which it may be manufactured (by taking orthogonal sawcuts in a block of material), an attractive option is to use a heat sink consisting of an array of square fins of width $w$ on a side. The spacing between adjoining fins would be determined by the width of the sawblade, with the sum of this spacing and the fin width designated as the fin pitch $S$. The method by which the heat sink is joined to the chip would determine the interfacial contact resistance, $R_{t, c^{*}}^{n}$ Consider a square chip of width $W_{c}=16 \mathrm{~mm}$ and conditions for which cooling is provided by a dielectric liquid with $T_{\infty}=25^{\circ} \mathrm{C}$ and $h=1500 \mathrm{~W} / \mathrm{m}^{2} \cdot \mathrm{K}$. The heat $\operatorname{sink}$ is fabricated from copper $(k=400 \mathrm{~W} / \mathrm{m} \cdot \mathrm{K})$, and its characteristic dimensions are $w=0.25 \mathrm{~mm}$, $S=0.50 \mathrm{~mm}, L_{f}=6 \mathrm{~mm}$, and $L_{b}=3 \mathrm{~mm}$. The prescribed values of $w$ and $S$ represent minima imposed by manufacturing constraints and the need to maintain adequate flow in the passages between fins.
(a) If a metallurgical joint provides a contact resistance of $R_{t, c}^{\prime \prime}=5 \times 10^{-6} \mathrm{~m}^{2} \cdot \mathrm{K} / \mathrm{W}$ and the maximum allowable chip temperature is $85^{\circ} \mathrm{C}$, what is the maximum allowable chip power dissipation $q_{c} ?$ Assume all of the heat to be transferred through the heat sink.
(b) It may be possible to increase the heat dissipation by increasing $w$, subject to the constraint that $(S-w) \geq 0.25 \mathrm{~mm}$, and/or increasing $L_{f}$ (subject to manufacturing constraints that $L_{f} \leq 10 \mathrm{~mm}$ ). Assess the effect of such changes.