For the circuit in Problem $3.23$ (page 147) replace $Q_{5}$ and $Q_{6}$ with a single diode-connected NMOS transistor $Q_{7}$ to generate the gate voltage of $Q_{2}$. Find the size of $Q_{7}$ to maximize the signal swing that can be obtained at the amplifier output, $\mathrm{v}_{0}$, while ensuring all transistors remain in active mode.