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Analog Integrated Circuit Design

Carusone, Tony Chan, Martin, Ken, Johns, David

Chapter 6

Basic Opamp Design And Compensation - all with Video Answers

Educators

Chapter Questions

01:54

Problem 1

For the two-stage opamp of Fig. 6.3, assume that the input bias current is reduced to $\mathrm{I}_{\mathrm{D} 8}=15 \mu \mathrm{A}$, all transistor sizes remain the same, and $\mathrm{C}_{\mathrm{c}}=2 \mathrm{pF}$.
a. Estimate the dc gain of the opamp.
b. Estimate the $-3-\mathrm{dB}$ frequency of the first stage.
c. Estimate the unity-gain frequency of the opamp.
d. Find the slew rate.

Varsha Aggarwal
Varsha Aggarwal
Numerade Educator
01:09

Problem 2

If all of the gate lengths in Fig. $6.3$ are increased to $0.4 \mu \mathrm{m}$, what is the resulting impact on
a. the dc gain of the opamp
b. the unity-gain frequency of the opamp

Jacob Shpiece
Jacob Shpiece
Numerade Educator
View

Problem 3

In the two-stage opamp of Fig. $6.3, \mathrm{C}_{\mathrm{c}}=0.5 \mathrm{pF}$.
a. What is the slew rate?
b. What circuit changes could be made to increase the slew rate by $30 \%$ while keeping $\omega_{\mathrm{t}}$ and $\mathrm{C}_{\mathrm{c}}$ unchanged?
c. What circuit changes could be made to increase the slew rate by $20 \%$ while keeping $\omega_{\mathrm{t}}$ and power consumption unchanged?

Eduard Sanchez
Eduard Sanchez
Numerade Educator
01:27

Problem 4

How should the sizes of $Q_{6}$ and $Q_{7}$ change in Problem $6.3$ to maintain zero systematic offset voltage?

Ajay Singhal
Ajay Singhal
Numerade Educator
01:34

Problem 5

Assume $Q_{7}$ of the two-stage opamp in Fig. $6.3$ is widened to $21 \mu \mathrm{m}$ wide, and everything else remains the same. Estimate the inherent input-offset voltage.

Narayan Hari
Narayan Hari
Numerade Educator
01:27

Problem 6

Ignoring the body effect, what is the output voltage range of the opamp of Fig. $6.3$ ? What is the range of acceptable common-mode input voltage, assuming a $1.8-\mathrm{V}$ power supply is used?

Ajay Singhal
Ajay Singhal
Numerade Educator
02:47

Problem 7

Repeat Problem $6.6$, but take the body effect into account and find approximate answers. Assume the body terminals of $Q_{1,2}$ are connected to $V_{D D}$, $\Phi f \approx 0.4$ and $Y=0.3 \mathrm{~V}^{-1 / 2}$

IL
Isaac Linn
Numerade Educator
02:58

Problem 8

Assume the two-stage opamp of Fig. $6.3$ is connected with a resistive feedback network, as shown in
Fig. P6.8. If $\mathrm{V}_{\text {in }}=0.5 \mathrm{~V}$, how much current flows through $\mathrm{R}_{2}$ ? Hence, what is the remaining current flowing through $Q_{7}$ ? Estimate the effect of this on the transconductance $g_{m 7}$ and the second pole frequency, $\omega_{p 2}$.

Narayan Hari
Narayan Hari
Numerade Educator
06:54

Problem 9

A two-stage opamp with compensation capacitor has an equivalent second-pole frequency of $60 \mathrm{MHz}$. Assume the input transistors of the first stage have a transconductance of $3 \mathrm{~mA} / \mathrm{V}$ and that there is an output buffer with a gain of exactly unity. What is the required size of the compensation capacitor if the phase margin is to be $55^{\circ}$ for the feedback configuration shown in Fig. P6.8?

Ceren Uzun
Ceren Uzun
Texas Tech University
02:24

Problem 10

For the result of Problem $6.9$, what is a near-optimum size for a capacitor to be placed in parallel with $\mathrm{R}_{2}$ in order to obtain lead compensation?

Eric Mockensturm
Eric Mockensturm
Numerade Educator
06:06

Problem 11

You are to compensate the two-stage opamp of Fig. $6.3$ when driving a load capacitance of $C_{L}=5 \mathrm{pF}$.
a. Following the procedure in section $6.2 .2$, select the values of $C_{C}$ and $R_{C}$ in the compensation network assuming a unity-gain feedback configuration.
b. Keeping the same values of $C_{C}$ and $R_{C}$ as in part (a), what is the maximum load capacitance that can be driven while maintaining at least $60^{\circ}$ phase margin?
c. Modify $\mathrm{C}_{\mathrm{C}}, \mathrm{R}_{\mathrm{C}}$, and $\mathrm{W}_{1,2}$ to increase the slew rate by $30 \%$ while maintaining the same phase margin and total

Ze-Han Lee
Ze-Han Lee
Numerade Educator
05:46

Problem 12

Assume a two-stage opamp has been optimally compensated for a noninverting closed-loop gain of 4 (i.e., $\beta=0.25$ ) using the procedure in section $6.2 .2$ so that the equivalent second pole is $43 \%$ above the unity-gain frequency, $\omega_{\text {eq }}=1.43 \omega_{\mathrm{t}}$, and the lead compensation zero is $70 \%$ above the unity-gain frequency, $\omega_{\mathrm{z}}=1.7 \omega_{\mathrm{t}}$.
What is the phase margin if the feedback network is modified to provide a closed-loop gain of $2($ i.e., $\beta=0.5)$ ? What about a unity-gain configuration $(\beta=1)$ ?

Khoobchandra Agrawal
Khoobchandra Agrawal
Numerade Educator
01:54

Problem 13

It is desired to increase the width, and hence drain currents, of $Q_{6,7}$ in the two-stage opamp of Fig. $6.3$ in order to improve the amplifier's bandwidth. Assuming a load capacitance of $1 \mathrm{pF}$, estimate the width of $Q_{6,7}$ required to provide a second pole frequency of $300 \mathrm{MHz}$.

Ajay Singhal
Ajay Singhal
Numerade Educator
04:51

Problem 14

Consider what happens when $Q_{9}$ is placed on the output side of $C_{C}$ in Fig. $6.10$ (rather than where it is shown). Explain why the resulting two-stage opamp circuit would then oscillate for large positive output values.

M Hassan Anwar
M Hassan Anwar
Numerade Educator
03:51

Problem 15

An opamp has an open-loop transfer function given by
$$
A(s)=\frac{A_{0}\left(1+\frac{s}{\omega_{z}}\right)}{\left(1+\frac{s}{\omega_{1}}\right)\left(1+\frac{s}{\omega_{2}}\right)}
$$
Assume $\mathrm{A}_{0}=10^{4}$ and $\omega_{2}=10^{8} \mathrm{rad} / \mathrm{s}$. The feedback network has a gain $\beta=0.5$. The frequency of the zero is $70 \%$ higher than the resulting open-loop unity-gain frequency, $\omega_{2}=1.7 \omega_{\mathrm{t}}$. Find $\omega_{1}$ and $\omega_{\mathrm{t}}$ so that the phase margin is $80^{\circ}$.

M Hassan Anwar
M Hassan Anwar
Numerade Educator
03:51

Problem 16

An opamp has an open-loop transfer function given by
$$
\mathrm{A}(\mathrm{s}) \cong \frac{\mathrm{A}_{0}\left(1+\mathrm{s} \tau_{\mathrm{z}}\right)}{\mathrm{s} \tau_{1}\left(1+\mathrm{s} \tau_{2}\right)}
$$
Find the transfer function of the closed-loop amplifier, assuming a feedback factor $\beta$ exists. Find approximate equations for the resonant frequency and the Q factor of the denominator of the transfer function of the closed-loop amplifier.

M Hassan Anwar
M Hassan Anwar
Numerade Educator
02:08

Problem 17

Prove that the frequencies of the first and second poles of the amplifier of Fig. $6.3$ are still given by (6.19) and (6.20), even when lead compensation is used (i.e., when $R_{C}$ is included).

Khoobchandra Agrawal
Khoobchandra Agrawal
Numerade Educator
01:17

Problem 18

Calculate the output impedance of the two-transistor diode-connected circuit shown in Fig. P6.18 using smallsignal analysis. Assume both transistors are in the active region, ignore the body effect, and assume $g_{m 1}=g_{m 2}$, $r_{d s 1}=r_{d s 2}$, and $g_{m} r_{d s}>>1$.

Chai Santi
Chai Santi
Numerade Educator
01:44

Problem 19

Assume $\mathrm{n}$ is chosen to be 1 in Fig. $6.12$ and all transistors are taken to be equal sizes, except $(\mathrm{W} / \mathrm{L})_{5}$ is chosen so that $\mathrm{V}_{\mathrm{DS} 3}=\mathrm{V}_{\mathrm{DS} 2}=\mathrm{V}_{\mathrm{eff} 3}+0.1 \mathrm{~V}$, where $\mathrm{V}_{\mathrm{eff}}$ is chosen to be $0.2 \mathrm{~V}$ for all transistors except $\mathrm{Q}_{5}$. Ignoring the body effect, find the required size for all transistors assuming they all have lengths equal to $0.3 \mu \mathrm{m}$. Assume that $I_{\text {bias }}=50 \mu \mathrm{A}$.

Chai Santi
Chai Santi
Numerade Educator
01:17

Problem 20

For the circuit in Problem $3.23$ (page 147) replace $Q_{5}$ and $Q_{6}$ with a single diode-connected NMOS transistor $Q_{7}$ to generate the gate voltage of $Q_{2}$. Find the size of $Q_{7}$ to maximize the signal swing that can be obtained at the amplifier output, $\mathrm{v}_{0}$, while ensuring all transistors remain in active mode.

Chai Santi
Chai Santi
Numerade Educator
04:45

Problem 21

What are the drain-source voltages of $Q_{3}$ and $Q_{4}$ from Problem $6.19$ if the lengths of $Q_{3}$ and $Q_{4}$ are decreased to $0.2 \mu \mathrm{m}$ to maximize speed?

Prabhat Tyagi
Prabhat Tyagi
Numerade Educator
01:43

Problem 22

Using small-signal analysis and ignoring the body effect, show that the circuit of Fig. $6.13$ has an output impedance given by $r_{\text {out }} \cong g_{m 1} r_{d s 1} r_{d s 2}(1+A)$.

Khoobchandra Agrawal
Khoobchandra Agrawal
Numerade Educator
02:09

Problem 23

A wide-swing cascode current mirror is shown in Fig. P6.23. Assuming all devices are identically sized ( W/L), derive an expression for the resistance $R_{1}$ in terms of the current $I_{\text {in }}$ and device parameters in order to ensure that $Q_{1}$ and $Q_{3}$ are in active mode. How should $R_{1}$ be chosen to provide $50 \mathrm{mV}$ of margin so that
$$
\mathrm{V}_{\mathrm{DS}, 1}=\mathrm{V}_{\mathrm{eff}, 1}+50 \mathrm{mV} ?
$$

Vishal Gupta
Vishal Gupta
Numerade Educator
02:24

Problem 24

Consider the compound transistor in Fig. $\mathrm{P} 6.24$. Transistor $\mathrm{Q}_{5}$ is in triode and $\mathrm{Q}_{6}$ is in active mode. Find the relationship between $\mathrm{V}_{\mathrm{x}}$ and $\mathrm{V}_{\mathrm{G}}$ in terms of $\mathrm{K}$ where $(\mathrm{W} / \mathrm{L})_{5}=\mathrm{K}(\mathrm{W} / \mathrm{L})_{6}$.

Amit Srivastava
Amit Srivastava
Numerade Educator
01:16

Problem 25

The resistor $R_{1}$ in Fig. $P 6.23$ can be replaced by the triode transistor $Q_{5}$ in the circuit of Fig. $P 6.24$. The result is the circuit shown in Fig. $\mathrm{P} 6.25$ [Sooch, 1985]. All devices are sized identically except for $\mathrm{Q}_{5}$ which is sized smaller by a factor $\mathrm{K}<1$. Find the value of $\mathrm{K}$ required to keep $\mathrm{Q}_{1,3}$ in active mode.

Chai Santi
Chai Santi
Numerade Educator
02:07

Problem 26

For the circuit shown in Fig. P6.26, using small-signal analysis, find the output impedance. Approximate this expression for large $A$ and compare this to the approximate expression without the amplifier (i.e., $A=0$ ).

M Hassan Anwar
M Hassan Anwar
Numerade Educator
05:33

Problem 27

For the circuit shown in Fig. $6.16$ with the $\mathrm{W} / \mathrm{L}$ ratios shown and assuming all lengths are $0.3 \mu \mathrm{m}$, estimate the output impedance. Assume that all current sources are ideal and that $I_{\text {in }}=7 I_{\text {bias }}$. Compare this to the output impedance of a wide-swing cascode current mirror where the gate of $Q_{1}$ was simply connected to a dc bias voltage that keeps $Q_{2}$ in active mode.

Khoobchandra Agrawal
Khoobchandra Agrawal
Numerade Educator
04:44

Problem 28

The folded cascode amplifier in Fig. P6.28, is to be designed using the process parameters for the $0.35-\mu \mathrm{m}$ process in Table 1.5. Assume the bias voltage of the input is such that the bias voltage of the output is $1.5 \mathrm{~V}$.
a. Find the device widths so that $\mathrm{V}_{\text {eff }}=0.3 \mathrm{~V}$ for all transistors except $\mathrm{Q}_{6}$ and $\mathrm{Q}_{11}$. Take $\mathrm{V}_{\text {eff-6 }}=\mathrm{V}_{\text {eff-11 }}=2.24 \mathrm{~V}_{\text {eff }}$. Take $\mathrm{I}_{\mathrm{D}}=0.25 \mathrm{~mA}$ for all transistors.
b. Find the bias voltages at all nodes and verfify that all transistors are in the active region. (Ignore the body-effect when calculating the nodal voltages.)
c. Find the impedance separately looking into the drain of $Q_{2}$ and looking into the drain of $Q_{4}$ and also the amplifier output impedance.
d. Find the amplifier gain.
e. Assuming the load capacitance is $0.25 \mathrm{pF}$ and dominates, what is the $-3 \mathrm{~dB}$ bandwidth of the the amplifier? What is the unity-gain frequency of the amplifier?

Narayan Hari
Narayan Hari
Numerade Educator
00:36

Problem 29

An OTA has $\mathrm{G}_{\mathrm{ma}}=5 \mathrm{~mA} / \mathrm{V}$ and a dc gain of $45 \mathrm{~dB}$. What is its output resistance, $\mathrm{r}_{\text {out }}$ ?

Ze-Han Lee
Ze-Han Lee
Numerade Educator
01:01

Problem 30

An OTA has a unity gain frequency of $50 \mathrm{MHz}$ and a dc gain of $65 \mathrm{~dB}$. What is its dominant pole frequency?

Luis Mendoza
Luis Mendoza
Numerade Educator
01:13

Problem 31

A folded cascode opamp is to be used in the feedback configuration of Fig. $6.23$ with $\mathrm{C}_{1}=4 \mathrm{pF}, \mathrm{C}_{2}=2 \mathrm{pF}$, and $\mathrm{C}_{\mathrm{p}}, \mathrm{C}_{\mathrm{c}}, \mathrm{C}_{\text {load }}$ all negligible. Assume the input differential pair transistors are to be biased with $\mathrm{V}_{\text {eff }, 1}=150 \mathrm{mV}$, and $80 \%$ of the total dc current dissipation is to flow through the input differential pair transistors. Estimate the total current consumption required to obtain a closed-loop 3-dB bandwidth of $60 \mathrm{MHz}$.

Chai Santi
Chai Santi
Numerade Educator
02:56

Problem 32

Augment the design of the folded-cascode opamp in Example $6.9$ to replace $I_{\text {bias }}$ with the wide-swing cascode bias circuit of Fig. $6.12$ where $\mathrm{n}=1$ and $\mathrm{I}_{\text {in }}=\mathrm{I}_{\text {bias }}=20 \mu \mathrm{A}$. Next, replace the tail current source $\mathrm{I}_{\text {bias } 2}$ with a NMOS transistor biased by the same wide-swing bias circuit. Finally, introduce additional circuitry to generate the required bias voltage $\mathrm{V}_{\mathrm{B} 1}$. Give the sizes of all transistors.

Chai Santi
Chai Santi
Numerade Educator
01:54

Problem 33

For the folded-cascode amplifier shown in Fig. 6.20, with the transistor sizes given in Table 6.1, $\mathrm{I}_{\text {bias, } 1}=20 \mu \mathrm{A}$, and $C_{L}=10 \mathrm{pF}$, find the unity-gain frequency and the slew rate.

Varsha Aggarwal
Varsha Aggarwal
Numerade Educator
02:34

Problem 34

For the folded-cascode amplifier shown in Fig. $6.20$, with the transistor sizes given in Table $6.1$, estimate the approximate frequency of the second pole caused by the parasitic capacitances at the drains of $Q_{1}$ and $Q_{2}$. Assume a $1.8-\mathrm{V}$ power supply is used, and the total supply current is $0.4 \mathrm{~mA}$ as in Example 6.9. To simplify matters, junction capacitances can be ignored. What should $\mathrm{C}_{\mathrm{L}}$ be to achieve $70^{\circ}$ phase margin? What would the corresponding unity-gain frequency and slew rate be?

Chai Santi
Chai Santi
Numerade Educator
04:36

Problem 35

For the amplifier of Problem $6.34$, find the load capacitance, $\mathrm{C}_{\mathrm{L}}$, for a $55^{\circ}$ phase margin. What size resistor should be used to provide lead compensation with $\omega_{\mathrm{z}}=1.7 \omega_{\mathrm{t}}$ ? What is the final phase margin? What is the final unitygain frequency and slew rate?

Mayukh Banik
Mayukh Banik
Numerade Educator
05:46

Problem 36

For the folded-cascode amplifier shown in Fig. $6.20$, assume the bias currents of $Q_{1}$ and $Q_{2}$ are $K$ times greater than the bias currents in $Q_{5}$ and $Q_{6}$. Assume the total bias current in the opamp, $I_{\text {total }}$, is determined by a specified power dissipation. Derive an equation for the unity-gain frequency in terms of $\mathrm{K}$ and $\mathrm{I}_{\mathrm{total}}$. Then show that the unity-gain frequency is maximized by taking $\mathrm{K}$ large.

Khoobchandra Agrawal
Khoobchandra Agrawal
Numerade Educator
04:34

Problem 37

Define $\mathrm{K}$ as in Problem $6.36$, but this time derive the dc gain terms of $\mathrm{K}$ and $\mathrm{I}_{\text {total }}$ and show that it is maximized by taking $\mathrm{K}$ large.

Declan Nell
Declan Nell
Numerade Educator
01:14

Problem 38

Modify all of the device sizes of the opamp designed in Example $6.9$ and compensated in Example $6.10$ so that the gate lengths are reduced to $L=0.3 \mu \mathrm{m}$, while all values of $V_{\text {eff }}$ and all drain currents are kept constant. What is the resulting effect on the opamp's dc gain, unity-gain frequency, and slew rate? Estimate the effect on the opamp's second equivalent pole frequency.

M Hassan Anwar
M Hassan Anwar
Numerade Educator
02:54

Problem 39

Derive an equation for the ratio of the unity-gain frequency of the folded-cascode amplifier of Fig. $6.20$ to the unity-gain frequency of the current-mirror opamp of Fig. $6.22$ in terms of $\mathrm{K}$ and $\mathrm{I}_{\text {total }}$ assuming both amplifiers have the same size input transistors, total power dissipation, and load capacitances. For the folded-cascode opamp, define $\mathrm{K}$ to be $\mathrm{I}_{\mathrm{D} 2} / \mathrm{I}_{\mathrm{D} 7}$. What is this ratio for $\mathrm{K}$ equal to 1,2 , and 4 ?

Nikhil Kumar Rajpurohit
Nikhil Kumar Rajpurohit
Numerade Educator
01:14

Problem 40

A current-mirror opamp is to be used in the feedback configuration of Fig. $6.23$ with $\mathrm{C}_{1}=4 \mathrm{pF}, \mathrm{C}_{2}=2 \mathrm{pF}$, and $C_{p}, C_{c}, C_{\text {load }}$ all negligible. Assume the input differential pair transistors are to be biased with $V_{\text {off }, 1}=150 \mathrm{mV}$, and $\mathrm{K}=3$. Estimate the total current consumption required to obtain a closed-loop 3-dB bandwidth of $60 \mathrm{MHz}$.
How does this result compare with that obtained for the folded cascode opamp in Problem $6.31$ ? What is the resulting slew rate?

M Hassan Anwar
M Hassan Anwar
Numerade Educator
02:44

Problem 41

Repeat Problem $6.40$, but this time assume the input differential pair devices are biased in subthreshold so that $g_{m 1} \approx q l_{D} / n k T$.

Janielle Madlansacay
Janielle Madlansacay
Numerade Educator
01:58

Problem 42

For the enhanced current-mirror circuit shown in Fig. P6.26, replace the amplifier A with the current-mirror opamp. Derive an expression for the output resistance, $R_{\text {out }}$ in terms of the constituent transistors' small signal parameters $\left(\mathrm{g}_{\mathrm{m}}, \mathrm{r}_{\mathrm{ds}}\right.$, etc. $)$

Narayan Hari
Narayan Hari
Numerade Educator
01:14

Problem 43

Resize transistors $Q_{8,10,12,14}$ in the current-mirror opamp of Example $6.11$ to make $\mathrm{K}=4$. What is the resulting impact on dc gain, unity-gain frequency, and slew rate?

M Hassan Anwar
M Hassan Anwar
Numerade Educator
03:12

Problem 44

Consider the current mirror opamp of Fig. $6.22$ with the device sizes listed in Table $6.3$ and $\mathrm{I}_{\mathrm{b}}=320 \mu \mathrm{A}$. What is the maximum value of $\mathrm{C}_{\mathrm{L}}$ for which a unity-gain frequency of $80 \mathrm{MHz}$ is provided? What is the resulting slew-rate?

João Gabriel Alencar Caribé
João Gabriel Alencar Caribé
Numerade Educator
01:14

Problem 45

It is desired to reduce the power consumption of the opamp in Problem $6.44$ by $20 \%$ while maintaining the same slewrate performance. Keeping all device lengths $L=0.2 \mu \mathrm{m}$ and all $V_{\text {eff }}$ the same, find new values for the device widths and $\mathrm{I}_{\mathrm{b}}$. For this new design, what is the maximum value of $\mathrm{C}_{\mathrm{L}}$ for which a unity-gain frequency of $80 \mathrm{MHz}$ is provided?

M Hassan Anwar
M Hassan Anwar
Numerade Educator
04:51

Problem 46

Consider the current-mirror opamp described in Example 6.11, in the feedback configuration shown in Fig. 6.23, with $C_{1}=1 \mathrm{pF}$ and $C_{2}=C_{C}=C_{\text {load }}=5 \mathrm{pF}$. What is the linear settling time for 1 percent accuracy?

M Hassan Anwar
M Hassan Anwar
Numerade Educator
02:29

Problem 47

For the case described in Example 6.12, and assuming a current-mirror opamp described in Example 6.11, also assume the input voltage is a 1-V step change. Would the opamp slew rate limit? If so, how close must the output voltage come to its final value before its output voltage rate of change is less than the slew rate? How long would this take? How much longer would be required for linear settling to 1 percent of the total voltage change at the output?

Nikhil Kumar Rajpurohit
Nikhil Kumar Rajpurohit
Numerade Educator
01:29

Problem 48

Consider the circuit shown in Fig. P6.48, where a high-output-impedance opamp is used. Capacitor $\mathrm{C}_{\mathrm{p}}$ is the parasitic capacitance at the opamp input, while $C_{\circ}$ is the output capacitance. Assuming linear settling, show that the optimal value for minimizing the time constant of this circuit is given by

Dominador Tan
Dominador Tan
Numerade Educator
02:13

Problem 49

Based on the results of Problem $6.48$, derive $\tau_{\min }$ for $M=1, C_{\circ}=1 \mathrm{pF}$, and $C_{p}=0.05 \mathrm{pF}$. Sketch $\tau$ for other values of $C_{1}$ between $0.1 \mathrm{pF}$ and $1 \mathrm{pF}$.

Khoobchandra Agrawal
Khoobchandra Agrawal
Numerade Educator
01:13

Problem 50

What are the single-ended slew rates of the fully differential folded-cascode and current-mirror opamps, assuming $\mathrm{K}=2$ and the current densities are the same as those of Example $6.9$ and Example $6.11$, respectively? Calculate the slew rates in both the positive and the negative directions. Assume the load capacitances are $10 \mathrm{pF}$ between each output and ground. For the folded-cascode design, assume the clamp transistors $Q_{11}$ and $Q_{12}$ of Fig. $6.28$ have not been included. Also, assume the current sources biasing the output stages do not change during transients.

Chai Santi
Chai Santi
Numerade Educator
06:22

Problem 51

Derive the slew rate of the fully differential opamp of Fig. $6.30$ in terms of $C_{L}, K$, and $I_{\text {bias. }}$

David Collins
David Collins
Numerade Educator
03:04

Problem 52

Derive an equation for the unity-gain frequency of the fully differential opamp shown in Fig. $6.31$ in terms of $\mathrm{K}$ and $\mathrm{I}_{\text {total }}$.

Narayan Hari
Narayan Hari
Numerade Educator
01:24

Problem 53

Derive expressions for the unity-gain frequency and slew rate of the fully differential opamp shown in Fig. $6.33$ in terms device parameters and sizes, component values, and the bias currents $\mathrm{I}_{1}, \mathrm{I}_{2}$, and $\mathrm{I}_{3}$.

Amit Srivastava
Amit Srivastava
Numerade Educator
01:13

Problem 54

Assume the CMFB circuit of Fig. $6.34$ has a $1.8$ - $\mathrm{V}$ power supply voltage, and that the current sources require $0.3 \mathrm{~V}$ across them in order to have all transistors remain in the active regions. Ignoring the body effect, what $\mathrm{V}_{\text {eff }}$ bias voltage should be used for the $\mathrm{p}$-channel transistors to maximize signal swing? What is the maximum single-ended signal swing before the gain of the common-mode feedback circuitry goes to zero and why?

Chai Santi
Chai Santi
Numerade Educator
01:39

Problem 55

Repeat Problem 6.54, but do not ignore the body effect. Assume the $\mathrm{n}$-wells of the $\mathrm{p}$-channel transistors are connected to $\mathrm{V}_{\mathrm{DD}}$.

Chai Santi
Chai Santi
Numerade Educator
01:56

Problem 56

For the circuit of Fig. 6.37, find an expression for the gain from $\mathrm{V}_{\text {cntrl }}$ to the output common-mode voltage, $\mathrm{V}_{\text {out, cm, }}$ in terms of the transistor small-signal parameters. If the common-mode sense and different amplifier circuits of Fig. $6.36$ are used in Fig. 6.37, find an expression for the loop gain.

Kajal Gautam
Kajal Gautam
Numerade Educator
01:06

Problem 57

A simple common-mode feedback circuit for a folded-cascode opamp is presented in Fig. P6.57. If the bias currents of all transistors are $\mathrm{I}_{\mathrm{D}}=100 \mu \mathrm{A}$ and device lengths are $\mathrm{L}=0.25 \mu \mathrm{m}$, choose the device widths $\mathrm{W}_{7-10}$ identically so that the output common-mode level is $0.8 \mathrm{~V}$. Next, select $\mathrm{V}_{\mathrm{B} 3}$ to maximize the available output signal swing.

Narayan Hari
Narayan Hari
Numerade Educator