Question

For the ECL circuit shown in Figure P14.41, plot the output voltages $V_{o 1}$ and $V_{o 2}$ as a function of the input voltage $V_i$ as it is swept from 0 to 5 volts. Assume $\beta_F=125$ and $V_{B E}=0.6 \mathrm{~V}$ for the transistors. Figure P14.41 can't copy

   For the ECL circuit shown in Figure P14.41, plot the output voltages $V_{o 1}$ and $V_{o 2}$ as a function of the input voltage $V_i$ as it is swept from 0 to 5 volts. Assume $\beta_F=125$ and $V_{B E}=0.6 \mathrm{~V}$ for the transistors.
Figure P14.41 can't copy
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Essentials of Electrical and Computer Engineering
Essentials of Electrical and Computer Engineering
David V. Kerns, Jr.,… 1st Edition
Chapter 14, Problem 41 ↓

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Step 1

Since the figure is not provided, assume that the ECL (Emitter Coupled Logic) circuit consists of two NPN transistors, Q1 and Q2, with their emitters connected together and biased with a current source. The input voltage \( V_i \) is applied to the base of Q1, and  Show more…

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For the ECL circuit shown in Figure P14.41, plot the output voltages $V_{o 1}$ and $V_{o 2}$ as a function of the input voltage $V_i$ as it is swept from 0 to 5 volts. Assume $\beta_F=125$ and $V_{B E}=0.6 \mathrm{~V}$ for the transistors. Figure P14.41 can't copy
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