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Essentials of Electrical and Computer Engineering

David V. Kerns, Jr., J. David Irwin

Chapter 14

Digital Electronic Logic Gates - all with Video Answers

Educators

Chapter Questions

02:53

Problem 1

(a) A logic gate has three input terminals. What is the number of possible input combinations to this logic circuit? (b) How does this change if one more input is added to the circuit?

N D
N D
Numerade Educator

Problem 2

Determine the truth table for the logic circuit shown in (a) Figure P14.2(a), (b) Figure P14.2(b).
Figure P14.2 can't copy

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Problem 3

Determine the truth table for the logic circuit shown in (a) Figure P14.3(a), (b) Figure P14.3(b).
Figure P14.3 can't copy

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02:01

Problem 4

(a) Construct the truth table for the circuit obtained by connecting together as a single input the two inputs of a NAND gate, as shown in Figure P14.4 (a). (b) Repeat (a) for a NOR gate, as shown in Figure P14.4(b).
Figure P14.4 can't copy

Nishant Kumar
Nishant Kumar
Numerade Educator

Problem 5

Construct the truth table for a three-input XOR-gate.

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Problem 6

The input and output waveforms of an inverter are shown in Figure P14,6. Obtain the values of $t_{P H L}, t_{P L H}$, and $t_P$ for the inverter.
Figure P14.6 can't copy

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Problem 7

If two inverters identical to the one in problem 14.6 are cascaded, what are the values of $t_{P L H}, t_{P H L}$, and $t_P$ for the combined circuit?

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Problem 8

(a) Construct a plot of the input and output waveform of an inverter similar to that in problem-14.6, but with $t_{P H L}=3 \mu \mathrm{s}$ and $t_P=5 \mu \mathrm{s}$. (b) What is the value of $t_{P L H}$ ?

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Problem 9

(a) Determine the rise and fall time of the signals shown in Figure P14.9 (a). (b) Repeat (a) for Figure P14.9 (b).
Figure P14.9 can't copy

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Problem 10

a) Construct a plot of the output waveform of an inverter similar to that in problem 14.9(a), with a rise time of $2 \mathrm{~ns}$ and a fall time of $0.5 \mathrm{~ns}$.

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Problem 11

a) Construct a plot of the output waveform of an inverter similar to that in problem 14.9(b), with a rise time of $4 \mathrm{~ns}$ and a fall time of $1 \mathrm{~ns}$.

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Problem 12

If four NAND gates each with an average propagation delay of $5 \mathrm{~ns}$ are connected in a serial path with three NOR gates each with a propagation delay of $4 \mathrm{~ns}$, what is the propagation delay of the entire circuit?

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Problem 13

A digital circuit has a clock frequency of 25 $\mathrm{MHz}$. The circuit uses gates with propogation delays $t_{P H L}=t_{P L H}=t_P=2 \mathrm{~ns}$. If data are presented at the input of a cascaded string of these gates at the leading edge of each clock cycle, what is the maximum number of gates that can be connected in series?

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Problem 14

Repeat problem 14.13 if the clock frequency is $100 \mathrm{MHz}$.

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Problem 15

Obtain the noise margins $N M_L$ and $N M_H$ for the gate whose transfer characteristic is shown in Figure P14.15
Figure P14.15 can't copy

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Problem 16

Calculate the noise margin, transition width, and logic swing of the gate whose input and output levels are shown in Figure P14.16
Figure P14.16 can't copy

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Problem 17

An NMOS inverter with a resistive load of $R_D=1.5 \mathrm{k} \Omega$ is shown in Figure P14.17. If $V_T=1.0 \mathrm{~V}$ and $r_{\text {on }}=100 \Omega$ in the ohmic region of MOSFET operation, obtain the values of $V_{O H}, V_{O L}, V_{I L}, V_{I H}, N M_L$, and $N M_H$ for the inverter. Assume $V_{I L}=V_{I H}$.
Figure P14.17 can't copy

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01:08

Problem 18

Repeat problem 14.17 if $r_{o n}=50 \Omega$.

Kratika Bhadauria
Kratika Bhadauria
Numerade Educator

Problem 19

(a) Construct a circuit drawing using $n$-channel MOSFETs and resistive loads for a two-input AND gate. (b) Repeat (a) for a two-input OR gate.

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02:32

Problem 20

(a) Design a three-input NAND gate with passive loads; show the circuit drawing including all transistors and other elements. (b) Repeat (a) for a three-input NOR gate.

Adriano Chikande
Adriano Chikande
Numerade Educator

Problem 21

An NMOS inverter with an enhancementmode active load is shown in Figure P14.21. (a) If $V_T=0.8 \mathrm{~V}$ for both devices, determine $V_{O H}$ and $V_{I L}$. (b) If the resistance of the load device is $1.5 \mathrm{k} \Omega$, what value of $r_{o n}$ for the input device is required to obtain $V_{O L}=.3 \mathrm{~V}$ ?
Figure P14.21 can't copy

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03:18

Problem 22

For the inverter circuit in problem 14.21, $V_T=0.7 \mathrm{~V}$ and $V_{O L}$ is determined to be $0.2 \mathrm{~V}$. If the value of $r_{o n}$ for the input transistor is $120 \Omega$, find the values of $N M_L$ and the effective resistance of the load device.

Prachita Kush
Prachita Kush
Numerade Educator

Problem 23

For the NMOS inverter circuit given in Figure P14.21, sketch the voltage transfer curve, $V_o$ versus $V_i$. (Assume $V_T=0.8 \mathrm{~V}$ and $V_{I H}=2.1 \mathrm{~V}$.)

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Problem 24

(a) Draw the circuit diagram of a three-input NAND gate with enhancement-mode active loads and NMOS transistors. (b) Repeat (a) for a three-input NOR gate.

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Problem 25

The voltage transfer characteristics of an inverter are shown in Figure P14.25. (a) Draw the transfer characteristics of a circuit obtained by cascading two of these inverters. (b) Compare the noise margins of the cascade and a single inverter.
Figure P14.25 can't copy

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Problem 26

(a) Construct the truth table for the circuit shown in Figure P14.26(a). (b) Construct the truth table of the logic circuit shown in Figure P14.26(b). (c) Compare the results in (a) and (b).
Figure P14.26 can't copy

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Problem 27

(a) Draw the circuit diagram of a three-input CMOS NAND gate. (b) Repeat (a) for a threeinput CMOS NOR gate.

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Problem 28

Construct the truth table for the CMOS logic circuit given in Figure 14.28.
Figure P14.28 can't copy

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Problem 29

(a) Draw the complete circuit diagram for a CMOS AND gate. (b) Repeat (a) for a CMOS OR gate.

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Problem 30

Consider the CMOS inverter with transfer characteristics shown in Figure 14.19. Assuming $\mathrm{V}_{\mathrm{DD}}=5 \mathrm{~V}$, (a) determine approximate values for the noise margins in this circuit. (b) Compare the CMOS noise margins to those of the enhancement-mode load inverter shown in Figure 14.15,

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Problem 31

Compare and contrast the performance of TTL bipolar logic with CMOS logic based on the following criteria:
(a) logic levels
(b) switching speeds
(c) circuit density
(d) power consumption

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01:56

Problem 32

For the NPN transistor circuit shown in Figure P14.32, assume $V_{C E(S A T)}=0.2 \mathrm{~V}, V_{B E}=$ $0.7 \mathrm{~V}, \beta_F=50$. (a) Determine the minimum value of $V_i$ that saturates the transistor. (b) Determine the fanout when the output is high.
Figure P14.32 can't copy

Chai Santi
Chai Santi
Numerade Educator

Problem 33

Assume the transistors in Figure P14.33 have $\beta_{\mathrm{F}}=100 . V_{B E}=0.6 \mathrm{~V}$, and $V_{C E(S A T)}=0.1 \mathrm{~V}$; the diode has $V_F=0.6 \mathrm{~V}$. (a) Calculate $V_{I L}, V_{O L}$, and $V_{O H}$. (b) What is the forced beta, $\beta^*$, for $Q_2$ when the output is low? (c) Construct a truth table for this circuit.
Figure P14.33 can't copy

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Problem 34

Repeat problem 14.33 for the case where the $2 \mathrm{k} \Omega$ resistor is removed from the circuit.

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Problem 35

For the circuit in Figure P14.33, (a) calculate the current that flows to ground through an input when a single input is at a logic low state. (b) Calculate the base current into Q2 when the output is in a logic low state.

Lainey Roebuck
Lainey Roebuck
Numerade Educator

Problem 36

The transistor in the circuit in Figure P14.36 has $\beta_F=50$, and $V_{B E}=0.6 \mathrm{~V}$. Determine $V_o$, the collector, base, and diode currents for $V_i=4 \mathrm{~V}$. Assume a Schottky turn-on voltage $V_F=0.3 \mathrm{~V}$.
Figure P14.36 can't copy

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Problem 37

Figure P14.37 shows a two-input TTL NAND gate. The transistors are identical with high betas, $V_{B E}=0.7 \mathrm{~V}$ and assume $V_{C E(S A T)}=$ $0.25 \mathrm{~V}$; for the diode, assume $V_F=0.6 \mathrm{~V}$. Calculate $V_{O L}, V_{O H}$, and $V_{I L}$ for this circuit. Sketch the transfer characteristics of the circuit.
Figure P14.37 can't copy

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Problem 38

For the circuit in problem 14.37 , calculate the forced beta, $\beta^*$, for $Q_3$ if the output is in a low state, and $\beta_F$ for all transistors is assumed to be 100.

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Problem 39

Construct a truth table for the logic circuit in Figure P14.37.

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Problem 40

Repeat problem 14.37 if a load resistance of $300 \Omega$ is attached from the output to ground.

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Problem 41

For the ECL circuit shown in Figure P14.41, plot the output voltages $V_{o 1}$ and $V_{o 2}$ as a function of the input voltage $V_i$ as it is swept from 0 to 5 volts. Assume $\beta_F=125$ and $V_{B E}=0.6 \mathrm{~V}$ for the transistors.
Figure P14.41 can't copy

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Problem 42

Calculate the logic levels and noise margins of the ECL circuit with level shifter shown in Figure P14.42. Assume that the $\beta_F$ 's of the transistors are large, $V_{B E}=0.7 \mathrm{~V}$, and that $V_{I H}=V_{I L}$.
Figure P14.42 can't copy

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