Which of the following can cause a hazard for a pipelined...

Which of the following can cause a hazard for a pipelined CPU with a single ALU? (i) The $(j+1)^{\text {st }}$ instruction uses the result of the $j^{\text {th }}$ instruction as an operand. (ii) The $j^{\text {th }}$ and $(j+1)^{\text {st }}$ instructions require the ALU at the same time. (iii) The execution of a conditional jump instruction. (iv) The execution of non-conditional jump instruction. (A) (i) and (ii) (B) (ii) and (iii) (C) (i), (ii) and (iii) (D) (i), (ii), (iii) and (iv)

Which of the following can cause a hazard for a pipelined CPU with a single ALU?
(i) The $(j+1)^{\text {st }}$ instruction uses the result of the $j^{\text {th }}$ instruction as an operand.
(ii) The $j^{\text {th }}$ and $(j+1)^{\text {st }}$ instructions require the ALU at the same time.
(iii) The execution of a conditional jump instruction.
(iv) The execution of non-conditional jump instruction.
(A) (i) and (ii)
(B) (ii) and (iii)
(C) (i), (ii) and (iii)
(D) (i), (ii), (iii) and (iv)

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Key Concepts

Pipelining

Pipelining is an architectural technique used to execute multiple instruction stages concurrently, thereby improving throughput. It divides the processing of instructions into distinct stages, each handling a part of the instruction cycle. However, the overlapping execution can lead to hazards that must be managed to maintain efficient operations.

Control Hazard

A control hazard, often associated with branch instructions like conditional jumps, occurs when the flow of instruction execution is altered. The uncertainty regarding the target of the branch can result in pipeline stalls or incorrect prefetching of instructions until the branch decision is resolved.

Structural Hazard

A structural hazard arises when hardware resources are insufficient to support all active instructions simultaneously within the pipeline. In scenarios such as a pipelined CPU with a single ALU, if two instructions require the ALU concurrently, one instruction must wait, leading to a potential performance bottleneck.

Data Hazard

A data hazard occurs when an instruction depends on the output of a previous instruction that has not yet completed its execution in the pipeline. This dependency may lead to delays or the need for techniques such as data forwarding or stalling to ensure that the correct data is used in further computations.

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