I need the code and testbench for the given design with an elaborate explanation of an instruction and its operand. The meaning of the syntax RX [RY] is that the contents of register RY are loaded into register RX. The mv (move) instruction allows data to be copied from one register to another. For the mvi (move immediate) instruction, the expression RX D indicates that the 16-bit constant D is loaded into register RX.
Table 1. Instructions performed in the processor.
Each instruction can be encoded and stored in the IR register using the 9-bit format IIIXXXYYY, where III represents the instruction, XXX gives the RX register, and YYY gives the RY register. Although only two bits are needed to encode our four instructions, we are using three bits because other instructions will be added to the processor in later parts of this exercise. Hence IR has to be connected to nine bits of the 16-bit DIN input, as indicated in Figure 1. For the mvi instruction, the YYY field has no meaning, and the immediate data #D has to be supplied on the 16-bit DIN input after the mvi instruction word is stored into IR.
Some instructions, such as an addition or subtraction, take more than one clock cycle to complete because multiple transfers have to be performed across the bus. The finite state machine in the control unit "steps through" such instructions, asserting the control signals needed in successive clock cycles until the instruction has completed. The processor starts executing the instruction on the DIN input when the Run signal is asserted, and the processor asserts the Done output when the instruction is finished. Table 2 indicates the control signals that can be asserted in each time step to implement the instructions in Table 1. Note that the only control signal asserted in time step 0 is IR in, so this time step is not shown in the table.
Table 2. Control signals asserted in each instruction/time step.
Perform the following task:
Write RTL code using Verilog HDL and Perform simulation by writing testbench.
(Use VCS simulator)
Apply suitable timing, power, and area constraints and perform logic synthesis targeting SAED32nm Technology Library
Perform Timing Analysis using Prime Time Analyzer and Optimize the netlist for timing.
of an instruction and its operand. The meaning of the syntax RX [RY] is that the contents of register RY are loaded into register RX. The mv (move) instruction allows data to be copied from one register to another. For the mvi (move immediate) instruction, the expression RX D indicates that the 16-bit constant D is loaded into register RX.
Figure 1 shows a digital system that contains a number of 16-bit registers, a multiplexer, an adder/subtracter unit, and a control unit (finite state machine). Data is input to this system via the 16-bit DIN input. This data can be loaded through the 16-bit wide multiplexer into the various registers, such as R0, ..., R7. The multiplexer also allows data to be transferred from one register to another. The multiplexer's output wires are called a bus in the figure because this term is often used for wiring that allows data to be transferred from one location in a system to another. Addition or subtraction is performed by using the multiplexer to first place one 16-bit number onto the bus wires and loading this number into register 4. Once this is done, a second 16-bit number is placed onto the bus, the adder/subtracter unit performs the required operation, and the result is loaded into register G. The data in G can then be transferred to one of the other registers as required.
Operation Function performed mv Rx, Ry Rx [Ry] mvi RxD Rx D add Rx, Ry RxRx+Ry sub Rx, Ry Rx[Rx-[Ry]
Table 1. Instructions performed in the processor.
Each instruction can be encoded and stored in the IR register using the 9-bit format IIIXXXYYY, where III represents the instruction, XXX gives the RX register, and YYY gives the RY register. Although only two bits are needed to encode our four instructions, we are using three bits because other instructions will be added to the processor in later parts of this exercise. Hence IR has to be connected to nine bits of the 16-bit DIN input, as indicated in Figure 1. For the mvi instruction, the YYY field has no meaning, and the immediate data #D has to be supplied on the 16-bit DIN input after the mvi instruction word is stored into IR. Some instructions, such as an addition or subtraction, take more than one clock cycle to complete because multiple transfers have to be performed across the bus. The finite state machine in the control unit steps through such instructions, asserting the control signals needed in successive clock cycles until the instruction has completed. The processor starts executing the instruction on the DIN input when the Run signal is asserted, and the processor asserts the Done output when the instruction is finished. Table 2 indicates the control signals that can be asserted in each time step to implement the instructions in Table 1. Note that the only control signal asserted in time step 0 is IR in, so this time step is not shown in the table.
DIN
T1
T2
T3
(mv): b
RYout, RXs, Done (mvi): I DINout, RXn Done (add): RXoub Ain RYub Gin Gout, R.Xin. Done (sub): I3 RXout, Ain RYout, Gin, Gout, RX'm, AddSub Done
unit FSM
Table 2. Control signals asserted in each instruction/time step.
Figure 1: A digital system.
The system can perform different operations in each clock cycle, as governed by the control unit. This unit determines when particular data is placed onto the bus wires and it controls which of the registers is to be loaded with this data. For example, if the control unit asserts the signals Roor and At, then the multiplexer will place
Perform the following task
Write RTL code using Verilog HDL and Perform simulation by writing testbench. (Use VCS simulator)
A system like this is often called a processor. It executes operations specified in the form of instructions. Table 1 lists the instructions that the processor has to support for this exercise. The left column shows the name
2. Apply suitable timing, power, and area constraints and perform logic synthesis targeting SAED32nm Technology Library
3. Perform Timing Analysis using Prime Time Analyzer and Optimize the netlist for timing.
