Question

I need the code and testbench for the given design with an elaborate explanation of an instruction and its operand. The meaning of the syntax RX [RY] is that the contents of register RY are loaded into register RX. The mv (move) instruction allows data to be copied from one register to another. For the mvi (move immediate) instruction, the expression RX D indicates that the 16-bit constant D is loaded into register RX. Table 1. Instructions performed in the processor. Each instruction can be encoded and stored in the IR register using the 9-bit format IIIXXXYYY, where III represents the instruction, XXX gives the RX register, and YYY gives the RY register. Although only two bits are needed to encode our four instructions, we are using three bits because other instructions will be added to the processor in later parts of this exercise. Hence IR has to be connected to nine bits of the 16-bit DIN input, as indicated in Figure 1. For the mvi instruction, the YYY field has no meaning, and the immediate data #D has to be supplied on the 16-bit DIN input after the mvi instruction word is stored into IR. Some instructions, such as an addition or subtraction, take more than one clock cycle to complete because multiple transfers have to be performed across the bus. The finite state machine in the control unit "steps through" such instructions, asserting the control signals needed in successive clock cycles until the instruction has completed. The processor starts executing the instruction on the DIN input when the Run signal is asserted, and the processor asserts the Done output when the instruction is finished. Table 2 indicates the control signals that can be asserted in each time step to implement the instructions in Table 1. Note that the only control signal asserted in time step 0 is IR in, so this time step is not shown in the table. Table 2. Control signals asserted in each instruction/time step. Perform the following task: Write RTL code using Verilog HDL and Perform simulation by writing testbench. (Use VCS simulator) Apply suitable timing, power, and area constraints and perform logic synthesis targeting SAED32nm Technology Library Perform Timing Analysis using Prime Time Analyzer and Optimize the netlist for timing. of an instruction and its operand. The meaning of the syntax RX [RY] is that the contents of register RY are loaded into register RX. The mv (move) instruction allows data to be copied from one register to another. For the mvi (move immediate) instruction, the expression RX D indicates that the 16-bit constant D is loaded into register RX. Figure 1 shows a digital system that contains a number of 16-bit registers, a multiplexer, an adder/subtracter unit, and a control unit (finite state machine). Data is input to this system via the 16-bit DIN input. This data can be loaded through the 16-bit wide multiplexer into the various registers, such as R0, ..., R7. The multiplexer also allows data to be transferred from one register to another. The multiplexer's output wires are called a bus in the figure because this term is often used for wiring that allows data to be transferred from one location in a system to another. Addition or subtraction is performed by using the multiplexer to first place one 16-bit number onto the bus wires and loading this number into register 4. Once this is done, a second 16-bit number is placed onto the bus, the adder/subtracter unit performs the required operation, and the result is loaded into register G. The data in G can then be transferred to one of the other registers as required. Operation Function performed mv Rx, Ry Rx [Ry] mvi RxD Rx D add Rx, Ry RxRx+Ry sub Rx, Ry Rx[Rx-[Ry] Table 1. Instructions performed in the processor. Each instruction can be encoded and stored in the IR register using the 9-bit format IIIXXXYYY, where III represents the instruction, XXX gives the RX register, and YYY gives the RY register. Although only two bits are needed to encode our four instructions, we are using three bits because other instructions will be added to the processor in later parts of this exercise. Hence IR has to be connected to nine bits of the 16-bit DIN input, as indicated in Figure 1. For the mvi instruction, the YYY field has no meaning, and the immediate data #D has to be supplied on the 16-bit DIN input after the mvi instruction word is stored into IR. Some instructions, such as an addition or subtraction, take more than one clock cycle to complete because multiple transfers have to be performed across the bus. The finite state machine in the control unit steps through such instructions, asserting the control signals needed in successive clock cycles until the instruction has completed. The processor starts executing the instruction on the DIN input when the Run signal is asserted, and the processor asserts the Done output when the instruction is finished. Table 2 indicates the control signals that can be asserted in each time step to implement the instructions in Table 1. Note that the only control signal asserted in time step 0 is IR in, so this time step is not shown in the table. DIN T1 T2 T3 (mv): b RYout, RXs, Done (mvi): I DINout, RXn Done (add): RXoub Ain RYub Gin Gout, R.Xin. Done (sub): I3 RXout, Ain RYout, Gin, Gout, RX'm, AddSub Done unit FSM Table 2. Control signals asserted in each instruction/time step. Figure 1: A digital system. The system can perform different operations in each clock cycle, as governed by the control unit. This unit determines when particular data is placed onto the bus wires and it controls which of the registers is to be loaded with this data. For example, if the control unit asserts the signals Roor and At, then the multiplexer will place Perform the following task Write RTL code using Verilog HDL and Perform simulation by writing testbench. (Use VCS simulator) A system like this is often called a processor. It executes operations specified in the form of instructions. Table 1 lists the instructions that the processor has to support for this exercise. The left column shows the name 2. Apply suitable timing, power, and area constraints and perform logic synthesis targeting SAED32nm Technology Library 3. Perform Timing Analysis using Prime Time Analyzer and Optimize the netlist for timing.

I need the code and testbench for the given design with an elaborate explanation of an instruction and its operand. The meaning of the syntax RX [RY] is that the contents of register RY are loaded into register RX. The mv (move) instruction allows data to be copied from one register to another. For the mvi (move immediate) instruction, the expression RX D indicates that the 16-bit constant D is loaded into register RX.

Table 1. Instructions performed in the processor.
Each instruction can be encoded and stored in the IR register using the 9-bit format IIIXXXYYY, where III represents the instruction, XXX gives the RX register, and YYY gives the RY register. Although only two bits are needed to encode our four instructions, we are using three bits because other instructions will be added to the processor in later parts of this exercise. Hence IR has to be connected to nine bits of the 16-bit DIN input, as indicated in Figure 1. For the mvi instruction, the YYY field has no meaning, and the immediate data #D has to be supplied on the 16-bit DIN input after the mvi instruction word is stored into IR.

Some instructions, such as an addition or subtraction, take more than one clock cycle to complete because multiple transfers have to be performed across the bus. The finite state machine in the control unit "steps through" such instructions, asserting the control signals needed in successive clock cycles until the instruction has completed. The processor starts executing the instruction on the DIN input when the Run signal is asserted, and the processor asserts the Done output when the instruction is finished. Table 2 indicates the control signals that can be asserted in each time step to implement the instructions in Table 1. Note that the only control signal asserted in time step 0 is IR in, so this time step is not shown in the table.

Table 2. Control signals asserted in each instruction/time step.
Perform the following task:
Write RTL code using Verilog HDL and Perform simulation by writing testbench.
(Use VCS simulator)
Apply suitable timing, power, and area constraints and perform logic synthesis targeting SAED32nm Technology Library
Perform Timing Analysis using Prime Time Analyzer and Optimize the netlist for timing.
of an instruction and its operand. The meaning of the syntax RX [RY] is that the contents of register RY are loaded into register RX. The mv (move) instruction allows data to be copied from one register to another. For the mvi (move immediate) instruction, the expression RX D indicates that the 16-bit constant D is loaded into register RX.
Figure 1 shows a digital system that contains a number of 16-bit registers, a multiplexer, an adder/subtracter unit, and a control unit (finite state machine). Data is input to this system via the 16-bit DIN input. This data can be loaded through the 16-bit wide multiplexer into the various registers, such as R0, ..., R7. The multiplexer also allows data to be transferred from one register to another. The multiplexer's output wires are called a bus in the figure because this term is often used for wiring that allows data to be transferred from one location in a system to another. Addition or subtraction is performed by using the multiplexer to first place one 16-bit number onto the bus wires and loading this number into register 4. Once this is done, a second 16-bit number is placed onto the bus, the adder/subtracter unit performs the required operation, and the result is loaded into register G. The data in G can then be transferred to one of the other registers as required.
Operation Function performed mv Rx, Ry Rx [Ry] mvi RxD Rx D add Rx, Ry RxRx+Ry sub Rx, Ry Rx[Rx-[Ry]
Table 1. Instructions performed in the processor.
Each instruction can be encoded and stored in the IR register using the 9-bit format IIIXXXYYY, where III represents the instruction, XXX gives the RX register, and YYY gives the RY register. Although only two bits are needed to encode our four instructions, we are using three bits because other instructions will be added to the processor in later parts of this exercise. Hence IR has to be connected to nine bits of the 16-bit DIN input, as indicated in Figure 1. For the mvi instruction, the YYY field has no meaning, and the immediate data #D has to be supplied on the 16-bit DIN input after the mvi instruction word is stored into IR. Some instructions, such as an addition or subtraction, take more than one clock cycle to complete because multiple transfers have to be performed across the bus. The finite state machine in the control unit steps through such instructions, asserting the control signals needed in successive clock cycles until the instruction has completed. The processor starts executing the instruction on the DIN input when the Run signal is asserted, and the processor asserts the Done output when the instruction is finished. Table 2 indicates the control signals that can be asserted in each time step to implement the instructions in Table 1. Note that the only control signal asserted in time step 0 is IR in, so this time step is not shown in the table.
DIN
T1
T2
T3
(mv): b
RYout, RXs, Done (mvi): I DINout, RXn Done (add): RXoub Ain RYub Gin Gout, R.Xin. Done (sub): I3 RXout, Ain RYout, Gin, Gout, RX'm, AddSub Done
unit FSM
Table 2. Control signals asserted in each instruction/time step.
Figure 1: A digital system.
The system can perform different operations in each clock cycle, as governed by the control unit. This unit determines when particular data is placed onto the bus wires and it controls which of the registers is to be loaded with this data. For example, if the control unit asserts the signals Roor and At, then the multiplexer will place
Perform the following task
Write RTL code using Verilog HDL and Perform simulation by writing testbench. (Use VCS simulator)
A system like this is often called a processor. It executes operations specified in the form of instructions. Table 1 lists the instructions that the processor has to support for this exercise. The left column shows the name
2. Apply suitable timing, power, and area constraints and perform logic synthesis targeting SAED32nm Technology Library
3. Perform Timing Analysis using Prime Time Analyzer and Optimize the netlist for timing.

i need the code and testbench for the given design with an elaborate explanation of an instruction and its operand the meaning of the syntax rx ry is that the contents of register ry are loa 99294

Added by Alexandra C.

We constantly seem to be pricing ourselves out of some markets and not charging enough in others. Our pricing policy is pretty simple: we mark up our full manufacturing cost by 50%. That means a computer that costs us $2,000 to manufacture will sell for $3,000. Until now I thought this was a workable approach, but now I’m not so sure. Steve Works, CEO, Cortland Manufacturing, Inc. (CMI) Steve’s Controller, Sally Nomer, had just told him that she believed the computers might be priced inappropriately. Steve continued: When I was at Leland [School of Management] I focused most of my attention on operations and marketing, convinced that those were the keys to my successful career. Cost accounting was boring and not relevant. But now my accountant is telling me that I need to think about a new way to assign manufacturing overhead to products, and I don’t even know where to start! I never dreamed that some day my career would come to this. I wish I’d paid more attention to those classes so I could understand what is going on here. I’m lost. BACKGROUND CMI manufactures several different models of computers, distributed to retail outlets throughout the 50 states. The company is proud of the user-friendly computers it produces, in particular their graphics capability. CMI claims the superb graphics are what distinguish its products from competitors. CMI purchases raw materials in components and subassemblies made to its specifications from a very small group of highly reliable suppliers. It uses a single facility to house both manufacturing facility and administrative and sales offices. The factory workers operate three kinds of machines. Inspecting machines check the raw materials and test components and subassemblies to assure they are working to specifications. Soldering machines solder various components as necessary. Finally assembly machines put all the components and subassemblies together into finished computers. The processes can vary by computer model. Depreciation, maintenance and repairs on the three types of machines account for about 40% of CMI’s overhead cost. The remainder of the overhead is made up of labor involved in receiving and handling the raw materials, adjusting and setting up machines for each new batch of computers, and inspecting and packing finished computers for shipping. Additional costs include insurance and depreciation on handling equipment, supplies, and utilities. The actual manufacturing effort (soldering, inspecting and assembly) is primarily automated, so CMI uses very little direct labor. The company also operates on a lean production model, so almost no inventories exist at the end of any period. Most of the computers are sold in large orders to national electronic chains. However, the Cortland 2000 is not such a machine. It represents a recent effort by CMI to enter the scientific computing market. The quantity manufactured and sold of this machine is expected to be much lower than other models even when it gains its hoped-for market share. Fewer customers exist for this more sophisticated, powerful, high-priced machine. Nonetheless, Mr. Works has believed from the conception of this product that, when all manufacturing costs were considered, the Cortland 2000 would contribute a reasonable amount to CMI’s selling and administrative costs and profit. The name recognition it brought in its elite community should enhance sales of the more generally used computers. FINANCIAL INFORMATION CMI budgeted direct labor costs for 2010 at $60,000,000. Based on expected sales, the company estimated that raw material purchased and used would be $300,000,000. Manufacturing overhead was budgeted at $196,000,000. It is currently allocated to production on the basis of machine hours (MH). As mentioned above, computers are priced at full production cost plus a mark-up of 50%. EXHIBIT 1 shows the expected direct manufacturing costs for two of the company’s computers. The Cortland 1000 is a very popular computer with a large production and sales volume. By contrast, the Cortland 2000, described above, is a state-of-the-art scientific computer with several special features. In particular, the Cortland 2000 a. Uses a new processing chip imported from Sweden. b. Has special patented random access memory (RAM) that gives it extremely high input/output speed. c. Is manufactured in very small batches to assure uniform quality from one computer to the next, to satisfy the users of the machines who have very high expectations for the performance of the machines they purchase. Mr. Works’ concerns arose when Ms. Nomer told him that she thought the company’s traditional overhead allocation system was providing misleading cost information about the different types of products. She developed an analysis of the 2010 manufacturing overhead costs, shown in EXHIBIT 2. She classified the overhead costs described above into activities. She also gathered data, shown in EXHIBIT 3, for the 2010 production of the Cortland 1000 and the Cortland 2000. Mr. Works commented on the data: I don’t know quite what to make of all this. Clearly I need some further explanation and analysis. I guess what I really need is some sense of what is the true manufacturing cost of each computer. I thought I knew that, but I didn’t really. Even though we cannot at this point change prices for 2010, we at least need to know if we’re covering full production cost on the Cortland 2000 and have something left to contribute to the company’s selling, general and administrative expenses. I thought this was so, but now … well, I’m not so sure. We’d better figure this out before we begin our budget cycle for 2011. Maybe I need to go back to school! EXHIBIT 1 Direct Manufacturing Costs for ONE Computer Cortland 1000 Cortland 2000 Direct Material $1,000 $2,500 Direct Labor $200 $400 EXHIBIT 2 Analysis of 2010 Budgeted Manufacturing Overhead Costs Activity Cost driver Budgeted activity (for entire company) Budgeted cost Receive/handle raw material Orders received 200 orders $90,000,000 Adjust/set up machines Number of setups 2,000 setups $12,000,000 Inspect, pack, ship computers Batches 500 batches $60,000,000 Inspect raw materials Inspection hours 200,000 insp. hr. $10,000,000 Solder parts Soldering hours 200,000 sdr. hr. $12,000,000 Assemble computers Assembly hours 100,000 assm. hr. $12,000,000 Total overhead $196,000,000 EXHIBIT 3 Production Data for Cortland 1000 and Cortland 2,000 Computers Item Measure Cortland 1000 Cortland 2000 Budgeted production Number of computers 20,000 5,000 Received order size* Size of order 10,000 500 Batch size Number of computers 5,000 100 Machine setups Number of s/u per batch 5 6 Inspecting time (Raw mat.) Hours / computer 1 2 Soldering time Hours / computer 3 1 Assembly time Hours / computer 1 1 * “Received order size” is the number of computers one order of raw materials will build. Thus, for example, (see above) the company receives 2 orders of raw materials for the Cortland 1,000. Calculation: 20,000 computers per year, divided by 10,000 computers each order will build = 2 orders per year. REQUIRED: Don’t try to begin answering questions until you have studied the case information carefully. Careless reading will result in careless errors! Just take a few extra minutes to understand it all. 1. Calculate the predetermined overhead rate the company is currently using. (Where should you look for the machine hours?) 2. Using the information from the exhibits and Q1, calculate the manufacturing cost of ONE Cortland 1000 and ONE Cortland 2000. 3. Calculate the selling price, under the current system, of ONE Cortland 1000 and ONE Cortland 2000. 4. Next, you are going to begin to analyze the ABC system. In order to do this, however, your study of Exhibits 2 and 3 should have told you that you are going to have to convert the information the company currently measures into the information you need for the ABC analysis. First, how many raw material orders did the company receive for each model? 5. How many batches of each model did the company pack and ship? 6. How many machine setups does Cortland do for each model? 7. Calculate a rate for each activity in Exhibit 2. 8. Use the rates calculated in Q7 to apply overhead to each product line: Cortland 1000 and 2000. 9. Calculate the overhead per computer for a Cortland 1000 and a Cortland 2000. 10. Calculate the manufacturing cost of ONE Cortland 1000 and ONE Cortland 2000 using ABC overhead allocation. 11. Show how the company would determine a selling price for each model under the ABC system. 12. Should Mr. Works adopt an ABC system for internal analysis? Your answer should address the question very specifically to this case – no generalities about ABC from the book. It should contain two points in favor of ABC, and two drawbacks that he should be aware of. 13. Mr. Works is also concerned about future product development. They have several new models under development at this time. If an ABC system is used, list two characteristics of a new model that will make it more costly to manufacture.

Sri K.

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