4. Design a count sequence, which has 32 different 8-bit values, in which exactly three bits change going from each
count state to the next in the sequence. This property is to be preserved when the counter goes from the 32nd
count state back to the first count state, which is to be the reset state "00000000". The state bits of the counter are
to be labelled Q7, Q6, Q5, Q4, Q3, Q2, Q1 and Q0. Provide a hardware diagram that illustrates how your count
sequence could be implemented using up to nine 8x1 multiplexers, nine flip-flops with asynchronous clear inputs,
and multiple inverters. Your counter design is to have a synchronous enable input, EN, and an asynchronous
active-high clear input, CLR.
Hint: To simplify the design, the eight counter bits should be partitioned into a more significant nibble (MSN),
Q7...Q4, and and a less significant nibble (LSN), Q3...Q0. By adopting this design constraint, the three bits that
change can be constrained, alternately, first to the MSN and then to the LSN. Then the design problem is
simplified to creating a 4-bit count sequence, which can be used independently for both the MSN and LSN, where
exactly three bits change when going from each 4-bit value to the next. Design the required 4-bit sequence so that
it starts at 0000 and then ends up back at 0000. [25 marks]
