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Erik Bartells

Erik B.

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Breanna Ollech verified

Numerade educator

For the path below, determine which latches borrow time and if any setup time violations occur. Repeat for cycle times of 1200, 1000, and 800 ps. Assume there is zero clock skew and that the latch delays are accounted for in the propagation delay, and ?1 = 300 ps; ?2 = 900 ps; ?3 = 200 ps; ?4 = 350 ps.

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INSTANT ANSWER

( ): The associated sub-circuit of the critical path in the CPA circuit below is those in light greys (or colored in red). ( ): A Kogge-Stone adder suffers a drawback of maximum fanout than all the other tree adders. ( ): A Sklansky adder suffers a drawback of maximum number of tracks than all the other tree adders. ( ): The basic logic multiplier consists of multiple CSA rows shifted by funnel shifter and a CPA array in the last shifted row. ( ): A carry save adder is in fact an extended full adder summing 3 inputs and then producing 2 outputs ( ): Flash is one kind of non-volatile memories. ( ): The operation of write for a SRAM cell includes a pre-charge stage. ( ): N1 being designed much smaller than \( \mathrm{N} 2 \) is for a valid read.

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ANSWERED

Breanna Ollech verified

Numerade educator

True and False Questions: (2 pt each) ( ): If hold times are violated (race condition), the functionality of the designed circuit fails. ( ): If setup times are violated (race condition), the functionality of the designed circuit definitely fails. ( ): Out of the three sequencing techniques, the 2-Phase Transparent Latches enjoys the best clock skew tolerance but less time-borrowing space. ( ): Buffers can be utilized to slow down signals if hold time is at risk. ( ): With the existence of glitches, the propagation delay is larger than contamination delay. ( ): The carry skip adder is guaranteed faster than the basic carry ripple adder. ( ): All the devices in the framed sub-circuit at the left part of a full adder circuit below are sized smallest possible (instead if P-N matched) to increase propagation speed. ( ): Both two circuit below designed for deriving sum in a full adder. The left one enjoys less power.

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