Write Verilog code to design an 8-bit unsigned division module. It should have the following ports: • Inputs: – clk – reset – divisor: 8-bits – dividend: 8-bits – ready: 1-bit • Outputs: – quotient: 8-bits – done: 1-bit The division operation should only be performed by Euclidean division (division by repeated subtraction). You are allowed to try to write this however you see fit, provided it meets the following specs: • Must use a finite state machine • Starts dividing once the "ready" signal is set to logic 1. Otherwise, reads "divisor" and "dividend" values from the user when the "ready" signal is 0. • Sets the "done" signal to logic 1 once division is completed, and outputs the correct quotient. "done" signal is set back to 0 when user sets "ready" back to zero. • If the divisor is zero, the quotient should be zero. Write a testbench to verify the functionality of the design for at least 5 different examples of your choice. Test cases should show proper functionality of the division itself, as well as the ready and done signals.