1
2 3 4 5 6 7 8 9 10
Time (cycles)
add s8, s4, s5
IM add RF s4 s5 DM s8 RF
sub s2, s8, s3
IM sub RF s8 s3 DM s2 RF
or s9, t6, s8
IM or RF t6 s8 DM s9 RF
and s7, s8, t2
IM and RF s8 t2 DM s7 RF
Figure 6
Based on Figure 6 for pipelined processor operation, please answer the questions below:
a. Indicate if instruction 2, 3, and 4 will produce the correct outputs? Give a reason for your
answer.
b. What type/category of hazard is this? What fixes or solution can be implemented to ad-
dress this hazard?
