7. Memory hierarchy more
(a) Assume that the cache block size is 20 words, and cache miss penalty consists of the followings:
address transfer:1 clock cycle DRAM access: 20 clock cycles data transfer: 2 clock cycles
Compute the miss penalty in the interleaved memory system with 5 memory banks. Also compute the memory bandwidth in this system
(b) Consider the following series of word address references: 1, 4, 8, 5, 20, 17, 19, 56, 9, 11, 4, 43 Assume that a 2-way set associative cache is used and the capacity of the entire cache is 8 words with one word per block. The cache is initially empty, and the LRU replacement policy is used.
Answer how many hits are made:
(c) Consider a virtual memory system with the following properties: 42-bit virtual address (byte address) 8-KB page size 32-bit physical address (byte address)
What is the total size of the page table for each process on this machine? Assume that each entry of the page table contains a valid-bit and a physical page number.
What is the total virtual memory size of each process?
What is the total physical memory size for each process?
