Consider a system with 256K bytes of physical memory, the size of each page is 64K bytes,
and the virtual address space is 1M. The system is byte-addressable. The processor has a 2
entry TLB and a 16Kbyte 2-way set associative cache with 512 bytes per block. An LRU
replacement strategy is implemented on both of the TLB and physical memory levels. The
following tables describe the current state of the memory system.
TLB
Virtual page Frame
Page Table Frame
Validity bit
(physical)
(physical)
0
1
0x5
OXA
2
3
0
1
2
3
0
1
TLB LRU
4
5
5
2
1
A
6
7
8
9
MEM LRU
A
3
1
B
C
1
1
A
B
D
3
F
1. Show the breakdown of the virtual address.
2. Show the breakdown of the physical address.
3. Show the breakdown of the physical address as interpreted by the cache system.
4. Calculate the physical address for the 0xC4620 virtual address.
5. Calculate the tag, set, and offset used to locate the above address (in 4) in the cache.
6. Illustrate the different actions involved in accessing the above address (in 4). Indicate the
changes applied to the TLB, page table, and the two LRU stacks.
