library IEEE; use IEEE.STD_LOGIC_1164.all
entity CET3198FE is
port (clk, reset, a, b: in STD_LOGIC;
q: out STD_LOGIC);
end CET3198FE;
architecture synth of CET3198FE is
type statetype is (S0, S1, S2);
signal state, nextstate: statetype;
begin
process (clk, reset)
begin
if reset then state <= S0;
elsif rising_edge(clk) then
state <= nextstate;
end if;
end process;
process (a, b, state) begin
case state is
when S0 =>
if a then
nextstate <= S1;
else nextstate <= S0;
end if;
when S1 =>
if b then
nextstate <= S2;
else nextstate <= S0;
end if;
when S2 =>
nextstate <= S0;
when others =>
nextstate <= S0;
end case;
end process;
q <= '1' when state = S2 else '0';
end synth;
The VHDL code given above implements:
Note: Mark all answers that apply.
A Mealy FSM
A Moore FSM
A synchronous circuit that can be implemented with two flip-flops
A synchronous circuit that can be implemented with at leas three flip-flops
A synchronous circuit that can not be implemented in real life.
