- (22 pts) Draw all necessary components for Datapath and 64 x 8 Register file A.
Note: Be sure to explicitly list all inputs, outputs along with their respective sizes in your design for each Datapath component.
The register file has only 1 READ port and 1 WRITE port. Draw the register file module with appropriate inputs/outputs and bit width.
- (14 pts) Draw FSM diagram of the controller (no need to write its Boolean equations)
Input: A[64][8], go (1-bit)
Output: A[64][8], done (1-bit)
SO
go'
go
min = 255
i=1
S1
S6
!(i <64)
S2
A[0] = min
i < 64
A[i] < min
S4
S3
min = A[i]
!(A[i] <min)
S5
i=i+1