00:01
Hello students, in this question, we know that lw instruction is dependent on the previous sw instruction because it reads from memory at the same address.
00:47
As a result, there is a structure hazard between these two instructions.
01:30
Now we will draw the pipeline.
01:35
Cycle then tell about the hazards.
01:39
Which cycle have hazard? i will represent only first 12 cycles.
01:50
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 instructions and stage.
02:10
This is a 5 stage pipeline.
02:15
So first instruction is sw, then lw, then subtract, then bqz, then add, now subtract.
02:34
Now there will be stall.
02:42
In cycle 8, the lw instruction requires data from memory during the mem stage...