Design a multicycle MIPS processor (datapath, ALU and control unit) for the instruction set given below. Refer to the MIPS reference sheet for the detailed operation of each instruction.
Mnemonic Instruction Name
lui Load upper immediate
slti Set less than immediate
jr Jump register
jal Jump and link
ori OR immediate
a. Provide a breakdown of each instruction into smaller steps so that each step is executed in one cycle. Also, design the ALU required by the processor.
b. Provide an incremental, step-by-step, design of the datapath i.e. in the first diagram, design the datapath for the first instruction lui, then (in a new diagram) add/remove connections and functional units to accommodate the second instruction slti in the datapath, then (in a new diagram) add/remove connections and functional units to accommodate the third instruction jr in the datapath, and so on. So, your datapath should consist of 5 incremental diagrams, like what we did it in the lecture slides. Your incremental datapath design should also include the necessary control signals for multiplexers, functional units, register enables etc.
c. Provide the state transition diagram for the control unit FSM of the multicycle processor.
NOTE: Your design should be optimized and should only include the functional units, datapath connections and control signals that enable the execution of the instruction set given in the table above. Do not include any unnecessary units/connections/control signals that are not required by the instruction set.