Question

3. (15%) While considering a 4-bit binary counter in Fig. 1 with functions in Table 3, please design three alternatives for a mod-7 counter (i.e., the counter evolves through a sequence of 7 distinct states), where \{I3, I2, I1, I0\} and \{A3, A2, A1, A0\} are data input and data output, respectively. (a) (5%) Use an AND gate and the load input. (b) (5%) Use the output carry (Cout), where Cout=1 if A3=A2=A1=A0=Count=1 and Load=0. [Hint: Consider the initial input value.] (c) (5%) Use a NAND gate and the asynchronous clear input. $I_3$ Load Count $A_3$ $I_2$ 4-Bit Binary $A_2$ $I_1$ Counter $A_1$ $I_0$ Clear CLK Cout $A_0$ Clear CLK Load Count Function 0 X X X Clear to 0 1 ? 1 X Load inputs 1 ? 0 1 Count next binary state 1 ? 0 0 No change Fig. 1. Block diagram of problem 3. Table 3: Function table for the counter of Fig. 1.

          3. (15%) While considering a 4-bit binary counter in Fig. 1 with functions in Table 3, please design
three alternatives for a mod-7 counter (i.e., the counter evolves through a sequence of 7 distinct
states), where \{I3, I2, I1, I0\} and \{A3, A2, A1, A0\} are data input and data output, respectively.
(a) (5%) Use an AND gate and the load input.
(b) (5%) Use the output carry (Cout), where Cout=1 if A3=A2=A1=A0=Count=1 and Load=0.
[Hint: Consider the initial input value.]
(c) (5%) Use a NAND gate and the asynchronous clear input.

$I_3$ Load Count $A_3$
$I_2$
4-Bit Binary
$A_2$
$I_1$
Counter
$A_1$
$I_0$ Clear CLK Cout $A_0$

Clear CLK Load Count Function
0 X X X Clear to 0
1 ? 1 X Load inputs
1 ? 0 1 Count next binary state
1 ? 0 0 No change
Fig. 1. Block diagram of problem 3. Table 3: Function table for the counter of Fig. 1.

3. (15%) While considering a 4-bit binary counter in Fig. 1 with functions in Table 3, please design
three alternatives for a mod-7 counter (i.e., the counter evolves through a sequence of 7 distinct
states), where {I3, I2, I1, I0} and {A3, A2, A1, A0} are data input and data output, respectively.
(a) (5%) Use an AND gate and the load input.
(b) (5%) Use the output carry (Cout), where Cout=1 if A3=A2=A1=A0=Count=1 and Load=0.
[Hint: Consider the initial input value.]
(c) (5%) Use a NAND gate and the asynchronous clear input.

I3 Load Count A3
I2
4-Bit Binary
A2
I1
Counter
A1
I0 Clear CLK Cout A0

Clear CLK Load Count Function
0 X X X Clear to 0
1 ? 1 X Load inputs
1 ? 0 1 Count next binary state
1 ? 0 0 No change
Fig. 1. Block diagram of problem 3. Table 3: Function table for the counter of Fig. 1.

Added by Lynn T.

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