Question

2. (50 points) Design a new kind of register that has the ability rotate its contents on every clock cycle. For example, rotating the data Q3Q2Q1Q0 leftwards by one-bit results in Q2Q1Q0Q3, rotating it twice yields Q1Q0Q3Q2, and so on. You will design a four-bit rotating register with a select input S1S0 and a data input D3D2D1D0. The register behaves according to the following table. S1 S0 Function 0 0 Load the data input D3D2D1D0 into the register. 0 1 Rotate the register's current contents leftwards by one-bit. 1 0 Rotate the register's current contents leftwards by two-bits. 1 1 Rotate the register's current contents leftwards by three-bits. a) (30 points) Draw a logic diagram to show how you can build this rotating register. Your design should include four D-type flip flops and 4 multiplexers. (Clearly denote the inputs CLK, S0, S1, D3, D2, D1, D0 and the outputs Q3, Q2, Q1, Q0.) b) (20 points) Fill in the following timing diagram for this register. The initial values of Q3Q2Q1Q0 are 0010. The initial values of D3D2D1D0 are 1100. S1S0 start at 01 and change as shown. You should assume positive edge-triggered flip-flops. (Assume there are no gate delays.) clock S1 S0 Q3 Q2 Q1 Q0

          2. (50 points) Design a new kind of register that has the ability rotate its contents on every clock cycle. For example, rotating the data Q3Q2Q1Q0 leftwards by one-bit results in Q2Q1Q0Q3, rotating it twice yields Q1Q0Q3Q2, and so on. You will design a four-bit rotating register with a select input S1S0 and a data input D3D2D1D0. The register behaves according to the following table.

S1 S0 Function
0 0 Load the data input D3D2D1D0 into the register.
0 1 Rotate the register's current contents leftwards by one-bit.
1 0 Rotate the register's current contents leftwards by two-bits.
1 1 Rotate the register's current contents leftwards by three-bits.

a) (30 points) Draw a logic diagram to show how you can build this rotating register. Your design should include four D-type flip flops and 4 multiplexers. (Clearly denote the inputs CLK, S0, S1, D3, D2, D1, D0 and the outputs Q3, Q2, Q1, Q0.)
b) (20 points) Fill in the following timing diagram for this register. The initial values of Q3Q2Q1Q0 are 0010. The initial values of D3D2D1D0 are 1100. S1S0 start at 01 and change as shown. You should assume positive edge-triggered flip-flops. (Assume there are no gate delays.)

clock
S1
S0
Q3
Q2
Q1
Q0

2. (50 points) Design a new kind of register that has the ability rotate its contents on every clock cycle. For example, rotating the data Q3Q2Q1Q0 leftwards by one-bit results in Q2Q1Q0Q3, rotating it twice yields Q1Q0Q3Q2, and so on. You will design a four-bit rotating register with a select input S1S0 and a data input D3D2D1D0. The register behaves according to the following table.

S1 S0 Function
0 0 Load the data input D3D2D1D0 into the register.
0 1 Rotate the register's current contents leftwards by one-bit.
1 0 Rotate the register's current contents leftwards by two-bits.
1 1 Rotate the register's current contents leftwards by three-bits.

a) (30 points) Draw a logic diagram to show how you can build this rotating register. Your design should include four D-type flip flops and 4 multiplexers. (Clearly denote the inputs CLK, S0, S1, D3, D2, D1, D0 and the outputs Q3, Q2, Q1, Q0.)
b) (20 points) Fill in the following timing diagram for this register. The initial values of Q3Q2Q1Q0 are 0010. The initial values of D3D2D1D0 are 1100. S1S0 start at 01 and change as shown. You should assume positive edge-triggered flip-flops. (Assume there are no gate delays.)

clock
S1
S0
Q3
Q2
Q1
Q0

Added by Alexis B.

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