Question

3. Write a structural VHDL model for an N-bit serial-in, serial-out shift register with inputs SI (serial input), EN (enable), and CK (clock), and a serial output (SO). Your model should include a generic in the entity declaration and a generate statement in the architecture. Assume that the following component for a D flip-flop with enable is available. component DFF port (D, EN, CK: in std_logic; Q: out std_logic); end component; a. Draw a block diagram and label all signals (internal and external). b. Write the VHDL model.

          3. Write a structural VHDL model for an N-bit serial-in, serial-out shift register with
inputs SI (serial input), EN (enable), and CK (clock), and a serial output (SO). Your
model should include a generic in the entity declaration and a generate statement in the
architecture. Assume that the following component for a D flip-flop with enable is
available.
component DFF
port (D, EN, CK: in std_logic;
Q: out std_logic);
end component;
a. Draw a block diagram and label all signals (internal and external).
b. Write the VHDL model.

3. Write a structural VHDL model for an N-bit serial-in, serial-out shift register with
inputs SI (serial input), EN (enable), and CK (clock), and a serial output (SO). Your
model should include a generic in the entity declaration and a generate statement in the
architecture. Assume that the following component for a D flip-flop with enable is
available.
component DFF
port (D, EN, CK: in stdlogic;
Q: out stdlogic);
end component;
a. Draw a block diagram and label all signals (internal and external).
b. Write the VHDL model.

Added by Steven F.

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