Question

4. Draw the pipeline diagram (see below) for the following code. LDR R1, [R2+50]; ADD R3, R1, R4; LDR R5, [R3+100]; ADD R6, R5, R7; STR R6, [R2+50]; load r1 from address 50+R2 R3 = R1 + R4 load R5 from address 100+R3 R6 = R5 + R7 store R6 at address 50+R2 Part A. Assume that there is no forwarding. How many cycles does it take to execute the above code segment? Indicate the total number of stall cycles. [5 points] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LDR R1, [R2+50] ADD R3, R1, R4 LDR R5, [R3+100] ADD R6, R5, R7 STR R6, [R2+50] Part B. Show the timing of this instruction sequence for the pipeline with normal forwarding hardware (full forwarding and 1st half write and 2nd half read are supported). [5 points] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LDR R1, [R2+50] ADD R3, R1, R4 LDR R5, [R3+100] ADD R6, R5, R7 STR R6, [R2+50]

          4. Draw the pipeline diagram (see below) for the following code.
LDR
R1, [R2+50];
ADD R3, R1, R4;
LDR R5, [R3+100];
ADD R6, R5, R7;
STR R6, [R2+50];
load r1 from address 50+R2
R3 = R1 + R4
load R5 from address 100+R3
R6 = R5 + R7
store R6 at address 50+R2
Part A. Assume that there is no forwarding. How many cycles does it take to execute the above code
segment? Indicate the total number of stall cycles. [5 points]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LDR R1, [R2+50]
ADD R3, R1, R4
LDR R5, [R3+100]
ADD R6, R5, R7
STR R6, [R2+50]
Part B. Show the timing of this instruction sequence for the pipeline with normal forwarding hardware (full
forwarding and 1st half write and 2nd half read are supported). [5 points]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LDR R1, [R2+50]
ADD R3, R1, R4
LDR R5, [R3+100]
ADD R6, R5, R7
STR R6, [R2+50]

4. Draw the pipeline diagram (see below) for the following code.
LDR
R1, [R2+50];
ADD R3, R1, R4;
LDR R5, [R3+100];
ADD R6, R5, R7;
STR R6, [R2+50];
load r1 from address 50+R2
R3 = R1 + R4
load R5 from address 100+R3
R6 = R5 + R7
store R6 at address 50+R2
Part A. Assume that there is no forwarding. How many cycles does it take to execute the above code
segment? Indicate the total number of stall cycles. [5 points]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LDR R1, [R2+50]
ADD R3, R1, R4
LDR R5, [R3+100]
ADD R6, R5, R7
STR R6, [R2+50]
Part B. Show the timing of this instruction sequence for the pipeline with normal forwarding hardware (full
forwarding and 1st half write and 2nd half read are supported). [5 points]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LDR R1, [R2+50]
ADD R3, R1, R4
LDR R5, [R3+100]
ADD R6, R5, R7
STR R6, [R2+50]

Added by Trevor C.

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