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6. Experimental work • Design the instruction memory and instruction register components in Verilog HDL. • Create the block diagram to connect the components as shown in figure below. a. Design a code in Verilog HDL and create the symbol of 32 bytes instruction memory (IM). (Refer to appendix how to create symbol). b. Save at least five different instructions inside the IM (use Verilog initial statement). c. Design a code in Verilog HDL and create the symbol of the Instruction Register (IR) unit, as shown in figure below. The unit should support sign extension. d. Add the below diagram and connect it to the PC unit you designed in the previous lab. e. Create waveform (University program VWF) to simulate and verify your block diagram. Your waveform should show the encoded fields of all instructions in the IM. 32 Read address 32 Instruction [31:0] Instruction memory Instruction Register Op (Instruction[31:26]) Rs (Instruction[25:21]) Rt (Instruction[20:16]) Rd (Instruction [15:11]) Shamt (Instruction[10:6]) Funct (Instruction[5:0]) 32-bits Sign Ext. Imm (Instruction[15:0]) 7. Thought Questions To be provided by your instructor during the Lab session. CE 437-Computer Design and Prototyping-Spring 2020 Page 6 of 7

          6. Experimental work
•	Design the instruction memory and instruction register components in Verilog HDL.
•	Create the block diagram to connect the components as shown in figure below.
a.	Design a code in Verilog HDL and create the symbol of 32 bytes instruction
memory (IM). (Refer to appendix how to create symbol).
b.	Save at least five different instructions inside the IM (use Verilog initial
statement).
c.	Design a code in Verilog HDL and create the symbol of the Instruction Register
(IR) unit, as shown in figure below. The unit should support sign extension.
d.	Add the below diagram and connect it to the PC unit you designed in the
previous lab.
e.	Create waveform (University program VWF) to simulate and verify your block
diagram. Your waveform should show the encoded fields of all instructions in
the IM.
32
Read
address
32
Instruction
[31:0]
Instruction
memory
Instruction Register
Op (Instruction[31:26])
Rs (Instruction[25:21])
Rt (Instruction[20:16])
Rd (Instruction [15:11])
Shamt (Instruction[10:6])
Funct (Instruction[5:0])
32-bits Sign Ext. Imm (Instruction[15:0])
7. Thought Questions
To be provided by your instructor during the Lab session.
CE 437-Computer Design and Prototyping-Spring 2020
Page 6 of 7

6. Experimental work
• Design the instruction memory and instruction register components in Verilog HDL.
• Create the block diagram to connect the components as shown in figure below.
a. Design a code in Verilog HDL and create the symbol of 32 bytes instruction
memory (IM). (Refer to appendix how to create symbol).
b. Save at least five different instructions inside the IM (use Verilog initial
statement).
c. Design a code in Verilog HDL and create the symbol of the Instruction Register
(IR) unit, as shown in figure below. The unit should support sign extension.
d. Add the below diagram and connect it to the PC unit you designed in the
previous lab.
e. Create waveform (University program VWF) to simulate and verify your block
diagram. Your waveform should show the encoded fields of all instructions in
the IM.
32
Read
address
32
Instruction
[31:0]
Instruction
memory
Instruction Register
Op (Instruction[31:26])
Rs (Instruction[25:21])
Rt (Instruction[20:16])
Rd (Instruction [15:11])
Shamt (Instruction[10:6])
Funct (Instruction[5:0])
32-bits Sign Ext. Imm (Instruction[15:0])
7. Thought Questions
To be provided by your instructor during the Lab session.
CE 437-Computer Design and Prototyping-Spring 2020
Page 6 of 7

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