Question

(8%) Consider the execution of the following code sequence on the five-stage pipelined processor: addi $9, $11, $12 sub $10, $11, $12 add $11, $6, $12 beq $11, $12, LABEL lw $11, 0 ($12) ... Exception _Handler: sw x26, 1000 (x0) ... (a) Suppose the forth instruction (beq) is detected to have a TLB miss in the IF stage (i.e., in clock 2/4 cycle 4), causing an exception. What instructions will appear in the IF, ID, EX, MEM, and WB stages, respectively, in clock cycle 5? (b) Suppose in clock cycle 5, an ALU malfunction exception occurs. What instructions will be in the IF, ID, EX, MEM, and WB stages, respectively, in clock cycle 6? (Note: Each instruction in your answer should be one chosen from the given instructions, or NOP.)

          (8%) Consider the execution of the following code sequence on the five-stage pipelined processor:
addi $9, $11, $12
sub $10, $11, $12
add $11, $6, $12
beq $11, $12, LABEL
lw $11, 0 ($12)
...
Exception _Handler: sw x26, 1000 (x0)
...
(a) Suppose the forth instruction (beq) is detected to have a TLB miss in the IF stage (i.e., in clock
2/4
cycle 4), causing an exception. What instructions will appear in the IF, ID, EX, MEM, and WB
stages, respectively, in clock cycle 5?
(b) Suppose in clock cycle 5, an ALU malfunction exception occurs. What instructions will be in the
IF, ID, EX, MEM, and WB stages, respectively, in clock cycle 6?
(Note: Each instruction in your answer should be one chosen from the given instructions, or NOP.)

8 consider the execution of the following code sequence on the five stage pipelined processor addi 9 11 12 sub 10 11 12 add 11 6 12 beq 11 12 label lw 11 0 12 exception handler sw x26 1000 92534

Added by Rachel G.

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