9.3.5 Design a VHDL behavioral model for a 4-bit serial bit sequence detector similar to Example 9.11. Use the entity definition provided in Fig. 9.3. Use the three-process approach to modeling FSMs described in this chapter for your design. The input to your sequence detector is called DIN, and the output is called FOUND. Your detector will assert FOUND anytime there is a 4-bit sequence of 0101. For all other input sequences, the output is not asserted. Model the states in your machine with a user-defined enumerated type.