Question

PROBLEM 2 A 3-bit parity checker counts the number of 1's in a sequence of 3 bits and outputs 1 if odd, 0 if even. (Example: If the input is 101, output is 0, but if the input is 001, output is 1). Knowing that: $V_{Tn} = 0.53 V$ $V_{Tp} = -0.51 V$ $\mu_n C_{ox} = 98.2 A/V^2$ $\mu_p C_{ox} = 46 A/V^2$ $V_{DD} = 1.2 V$ $E_{c,nL_n} = 0.45$ $E_{c,pL_p} = 1.2$ and the output load capacitance is 30fF: a) Draw the CMOS transistor-level of the complex logic gate. b) Compute the $(W/L)_n$ of the nMOS transistors such that the equivalent inverter of the complex logic gate has $t_{pd} = 20ps$ using the average method c) Draw the pseudo-nMOS transistor-level of the complex logic gate d) Compute the worst-case $V_{OL}$ of the equivalent inverter if $(W/L)_p = 4$ and $(W/L)_n = 1$.

          PROBLEM 2
A 3-bit parity checker counts the number of 1's in a sequence of 3 bits and outputs 1 if odd, 0 if
even. (Example: If the input is 101, output is 0, but if the input is 001, output is 1).
Knowing that:
$V_{Tn} = 0.53 V$
$V_{Tp} = -0.51 V$
$\mu_n C_{ox} = 98.2 A/V^2$
$\mu_p C_{ox} = 46 A/V^2$
$V_{DD} = 1.2 V$
$E_{c,nL_n} = 0.45$
$E_{c,pL_p} = 1.2$
and the output load capacitance is 30fF:
a) Draw the CMOS transistor-level of the complex logic gate.
b) Compute the $(W/L)_n$ of the nMOS transistors such that the equivalent inverter of the
complex logic gate has $t_{pd} = 20ps$ using the average method
c) Draw the pseudo-nMOS transistor-level of the complex logic gate
d) Compute the worst-case $V_{OL}$ of the equivalent inverter if $(W/L)_p = 4$ and $(W/L)_n = 1$.

PROBLEM 2
A 3-bit parity checker counts the number of 1's in a sequence of 3 bits and outputs 1 if odd, 0 if
even. (Example: If the input is 101, output is 0, but if the input is 001, output is 1).
Knowing that:
VTn = 0.53 V
VTp = -0.51 V
Cox = 98.2 A/V^2
Cox = 46 A/V^2
VDD = 1.2 V
Ec,nLn = 0.45
Ec,pLp = 1.2
and the output load capacitance is 30fF:
a) Draw the CMOS transistor-level of the complex logic gate.
b) Compute the (W/L)n of the nMOS transistors such that the equivalent inverter of the
complex logic gate has tpd = 20ps using the average method
c) Draw the pseudo-nMOS transistor-level of the complex logic gate
d) Compute the worst-case VOL of the equivalent inverter if (W/L)p = 4 and (W/L)n = 1.

Added by Walter D.

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