Create a VHDL code for a 3x3 array of storage units
Added by Henry G.
Step 1
Design a simple, parameterized VHDL module that implements a 3x3 array of storage units (registers). The array will support synchronous writes (on clock rising edge) to a single addressed cell and combinational reads from a single addressed cell. The data width is Show more…
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In this lab, you will design a simple calculator that only performs addition. The calculator adds two 4-bit numbers (A and B) and displays the result on the 8 LEDs. You will use the left four slide switches to enter the value for A and the right four slide switches for the value for B. The calculator also requires three push buttons BTN(2:0) on the FPGA board for the functions Add, AC, and Reset. When you press the push button for "Add", the calculator will display the result of A+B on the LEDs. When you press the push button for AC, the calculator will clear the result to zero and all the LEDs will turn off. The Reset button is used to reset the state machine to the initial state. Note that Reset is active high. Figure 1 shows the ASM chart for the calculator. Figure 2 shows the datapath circuit. Figure 1 - ASM chart Figure 2 - Datapath circuit
Akash M.
Design a 4-bit shift register with the following specifications: - An asynchronous active-low clear (ClrN) - A rising-edge triggered clock (CLK) - An active-high load signal (Ld) with parallel data input (D) - A function select signal (S) - When S = 0, the register shifts right with a serial data input (SI) - When S = 1, the register shifts right with sign extension (copy the sign bit) a) Draw the logic symbol and a truth table for the 4-bit shift register. b) Write a complete VHDL model (entity and behavioral architecture) for the 4-bit shift register. c) Write a VHDL testbench for the 4-bit shift register. Simulate the shift register for the following test sequence: - Load 0011 - Shift right 3 times with S = 0 and SI = 1 - Shift right 2 times with S = 0 and SI = 0 - Clear - Load 1100 - Shift right 2 times with S = 1 and SI = 0
Sri K.
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