Design a clamper circuit to clamp the upper limit of the input signal to 0.7 V (cf. Floyd, Example 2-13). Use a 4.7 kΩ resistor and a 1N4148 diode. Calculate the value of capacitance required (see Background below). Show your calculation. Then test your design in Multisim. Use a square wave input signal of 1.5 V amplitude and a frequency of 1 kHz. Run a transient simulation to show 10 periods of the output signal. Reduce the capacitor by a factor of 5 and repeat the simulation.