Question

Design and draw a sequential circuit having one input X and one output Y that implements the behavior shown in table 1.Name inputs and outputs of the circuit as shown in figure 1 (X, RST, clk, Y).State S0 should be coded as 00. Very important note: The VerilUOC_Desktop verifier requires that all inputs of the flip flops are connected to some value. So, it is necessary to connect "S" inputs to 0 and "load" inputs to 1. To do so, click in "wiring", select "Constant" and connect the constant (a logical 1) to the "load" inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the "S" inputs. Figure 1 estado actual | entrada X | estado siguiente | salida Z s0 | 0 | s1 | 0 s0 | 1 | s0 | 1 s1 | 0 | s2 | 0 s1 | 1 | s0 | 0 s2 | 0 | s2 | 0 s2 | 1 | s0 | 1 Table 1 Instructions to answer this question 1) In the virtual machine, open VerilUOC_Desktop and draw the circuit. 2) Click in "Simulate"->"Verification" and then click in the VerilCirc tab. 3) In "Module" select "Graded Exercises" and click on exercise 5.6.a. 4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.

          Design and draw a sequential circuit having one input X and one output Y that implements the behavior shown in table 1.Name inputs and outputs of the circuit as shown in figure 1 (X, RST, clk, Y).State S0 should be coded as 00.
Very important note: The VerilUOC_Desktop verifier requires that all inputs of the flip flops are connected to some value. So, it is necessary to connect "S" inputs to 0 and "load" inputs to 1. To do so, click in "wiring", select "Constant" and connect the constant (a logical 1) to the "load" inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the "S" inputs.
Figure 1
estado actual | entrada X | estado siguiente | salida Z
s0 | 0 | s1 | 0
s0 | 1 | s0 | 1
s1 | 0 | s2 | 0
s1 | 1 | s0 | 0
s2 | 0 | s2 | 0
s2 | 1 | s0 | 1
Table 1
Instructions to answer this question
1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.
2) Click in "Simulate"->"Verification" and then click in the VerilCirc tab.
3) In "Module" select "Graded Exercises" and click on exercise 5.6.a.
4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.

Design and draw a sequential circuit having one input X and one output Y that implements the behavior shown in table 1.Name inputs and outputs of the circuit as shown in figure 1 (X, RST, clk, Y).State S0 should be coded as 00.
Very important note: The VerilUOCDesktop verifier requires that all inputs of the flip flops are connected to some value. So, it is necessary to connect "S" inputs to 0 and "load" inputs to 1. To do so, click in "wiring", select "Constant" and connect the constant (a logical 1) to the "load" inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the "S" inputs.
Figure 1
estado actual | entrada X | estado siguiente | salida Z
s0 | 0 | s1 | 0
s0 | 1 | s0 | 1
s1 | 0 | s2 | 0
s1 | 1 | s0 | 0
s2 | 0 | s2 | 0
s2 | 1 | s0 | 1
Table 1
Instructions to answer this question
1) In the virtual machine, open VerilUOCDesktop and draw the circuit.
2) Click in "Simulate"->"Verification" and then click in the VerilCirc tab.
3) In "Module" select "Graded Exercises" and click on exercise 5.6.a.
4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.

Added by Jacob C.

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