Question

For the circuit below, assume a unit delay through the register and logic blocks (i.e., tclk-q = tlogic = 1). Assume that the registers, which are positive edge-triggered, have a set-up time tsu of 1 and a hold time of 0. The delay through the multiplexer tM equals 2. a) Determine the minimum clock period. Disregard clock skew. b) Repeat part (a), factoring in a nonzero clock skew. ? = t'? - t? = 1 c) Repeat part a, factoring in a nonzero clock skew ? = t'? - t? = 4 d) Derive the maximum positive clock skew that can be tolerated before the circuit fails. e) Derive the maximum negative clock skew that can be tolerated before the circuit fails.

          For the circuit below, assume a unit delay through the register and logic blocks (i.e., tclk-q = tlogic = 1). Assume that the registers, which are positive edge-triggered, have a set-up time tsu of 1 and a hold time of 0. The delay through the multiplexer tM equals 2.

a) Determine the minimum clock period. Disregard clock skew.

b) Repeat part (a), factoring in a nonzero clock skew.
? = t'? - t? = 1

c) Repeat part a, factoring in a nonzero clock skew
? = t'? - t? = 4

d) Derive the maximum positive clock skew that can be tolerated before the circuit fails.

e) Derive the maximum negative clock skew that can be tolerated before the circuit fails.

For the circuit below, assume a unit delay through the register and logic blocks (i.e., tclk-q = tlogic = 1). Assume that the registers, which are positive edge-triggered, have a set-up time tsu of 1 and a hold time of 0. The delay through the multiplexer tM equals 2.

a) Determine the minimum clock period. Disregard clock skew.

b) Repeat part (a), factoring in a nonzero clock skew.
? = t'? - t? = 1

c) Repeat part a, factoring in a nonzero clock skew
? = t'? - t? = 4

d) Derive the maximum positive clock skew that can be tolerated before the circuit fails.

e) Derive the maximum negative clock skew that can be tolerated before the circuit fails.

Added by Brandon B.

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