Introduction
The purpose of this laboratory is for the student to design (synthesize) a clocked synchronous finite state machine, and verify its operation in simulation. The student will invent their own state machine, and follow the design flow (process) to successfully create it.
Design Requirements
The clocked synchronous state machine must meet the following requirements:
4 States Only
1 Input Only
1 Output Only, or Output Coded State Assignment
D-Type Flip-Flops
All Circuits Minimized
Design
Using the techniques discussed in this cour date, design your circuit according to the design flow outlined below:
Write a Word Description of your state machine
One or two paragraphs maximum
A colleague should be able to create the State Diagram from your Written Description only
Create a State Diagram that represents the state machine in the word description
Your state diagram, and word description MUST match
Develop a State Table from the state diagram
Develop a Transition Table from the state table, and Include the Output Z
Develop K-Maps for each next state variable Q1, Q0°, and also for the Output Z
Develop Minimized Circuits for Q11°, Q0°, and also for the Output
Develop the Final Clocked Synchronous State Machine
Simulation
Verify your design in simulation
Conclusion
Given the process described above, what defines the successful completion of this laboratory? Did you achieve this? What challenges did you encounter?