Question

Problem 3.11 A. The verilog code in P3.11.v includes a modulo-5 counter using the structure discussed in the lecture. The counting sequence is Q[2:0] = 000, 001, 010, 011, 100, and wrapping back to 000. Show the block diagram with the register, the adder/incrementer, the load muxes, and the decoder logic. B. When the modulo-5 counter reaches Q[2:0] = 100, it enables a DFF shown in the following picture. Modify the verilog code of P3.11.v to include this logic. Show the modified code and its simulation waveform. C. If the frequency of clk is 1MHz, what is the frequency of clk_div? D. If the frequency of clk is 1MHz and if we want the frequency of clk_div to be 1KHz, • what modulo-n counter are we designing (i.e. what is the value of n)? • how many flip-flops at a minimum do we need for this modulo-n counter? • show the modified verilog code for this modulo-n counter. You don't need to simulate it.

          Problem 3.11
A. The verilog code in P3.11.v includes a modulo-5 counter using the structure
discussed in the lecture. The counting sequence is Q[2:0] = 000, 001, 010, 011, 100,
and wrapping back to 000. Show the block diagram with the register, the
adder/incrementer, the load muxes, and the decoder logic.
B. When the modulo-5 counter reaches Q[2:0] = 100, it enables a DFF shown in the
following picture. Modify the verilog code of P3.11.v to include this logic. Show the
modified code and its simulation waveform.
C. If the frequency of clk is 1MHz, what is the frequency of clk_div?
D. If the frequency of clk is 1MHz and if we want the frequency of clk_div to be 1KHz,
• what modulo-n counter are we designing (i.e. what is the value of n)?
• how many flip-flops at a minimum do we need for this modulo-n counter?
• show the modified verilog code for this modulo-n counter. You don't need to
simulate it.

Problem 3.11
A. The verilog code in P3.11.v includes a modulo-5 counter using the structure
discussed in the lecture. The counting sequence is Q[2:0] = 000, 001, 010, 011, 100,
and wrapping back to 000. Show the block diagram with the register, the
adder/incrementer, the load muxes, and the decoder logic.
B. When the modulo-5 counter reaches Q[2:0] = 100, it enables a DFF shown in the
following picture. Modify the verilog code of P3.11.v to include this logic. Show the
modified code and its simulation waveform.
C. If the frequency of clk is 1MHz, what is the frequency of clkdiv?
D. If the frequency of clk is 1MHz and if we want the frequency of clkdiv to be 1KHz,
• what modulo-n counter are we designing (i.e. what is the value of n)?
• how many flip-flops at a minimum do we need for this modulo-n counter?
• show the modified verilog code for this modulo-n counter. You don't need to
simulate it.

Added by Kristie B.

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