Q3: The following VHDL codes realize the Boolean equation "F = X and Y" in three different ways. They were labeled F1, F2, and F3. Explain the differences between these three descriptions/circuits.
library IEEE;
use IEEE.std_logic_1164.all;
entity hw3 is
port (
clock, reset: in std_logic;
X, Y: in std_logic;
F1, F2, F3: out std_logic
);
end hw3;
architecture DE1_SoC of hw3 is
begin
F1 <= X and Y;
hw3_demo: process (clock, reset)
begin
if (reset = '0') then
F2 <= X and Y;
F3 <= '0';
elsif rising_edge(clock) then
F3 <= X and Y;
end if;
end process;
end architecture DE1_SoC;