This is VHDL code. Make it into a flowchart.
BEGIN
-- Process begins either with a rising clock edge or start
PROCESS(clock, start)
BEGIN
-- If start is high, reset addition, average, sum, and count to zeros
IF start = 1 THEN
addition <= (others => '0');
average <= (others => '0');
sum <= (others => '0');
count <= 0;
-- Else if the clock is on its rising edge
ELSIF rising_edge(clock) THEN
-- If count is less than 8, increment count and update addition
IF (count < 8) THEN
-- Add num to current value of addition, and assign it back to addition
addition <= addition + num;
-- Increment count by 1
count <= count + 1;
-- Else, 8 numbers have now been added, update sum and average
ELSE
-- Assign the current value of addition to sum (outputs sum <= addition)
sum <= addition;
-- Shift addition to the right by 3 bits and assign it to average
average <= addition(10 DOWNTO 3);
END IF;
END IF;
END PROCESS;
END TypeArchitecture;