Question

1. (30 pts) Design a 3-bit counter with two low-active synchronous reset signals (resetn0 and resetn1) and a synchronous high-active enable control (en). The counting sequence is 0$\to$2$\to$4$\to$6$\to$0... or 1$\to$3$\to$5$\to$7$\to$1.... When resetn0 is low and resetn1 is high, reset to state 0; when the resetn0 is high and resetn1 is low, reset to state 1. Output z is same as the state. Hint: You may use Q<=Q+2 as the state transition equation because 6+2=0 and 7+2=1 for 3-bit additions. (a) (10 pts) Write the pseudo-code for the problem (b) (20 pts) Complete the Verilog design module mycounter01 (clock, resetn0, resetn1, en, z);

          1. (30 pts) Design a 3-bit counter with two low-active synchronous reset signals (resetn0
and resetn1) and a synchronous high-active enable control (en). The counting sequence is
0$\to$2$\to$4$\to$6$\to$0... or 1$\to$3$\to$5$\to$7$\to$1.... When resetn0 is low and resetn1 is high,
reset to state 0; when the resetn0 is high and resetn1 is low, reset to state 1. Output z is
same as the state. Hint: You may use Q<=Q+2 as the state transition equation because
6+2=0 and 7+2=1 for 3-bit additions.
(a) (10 pts) Write the pseudo-code for the problem
(b) (20 pts) Complete the Verilog design
module mycounter01 (clock, resetn0, resetn1, en, z);

1. (30 pts) Design a 3-bit counter with two low-active synchronous reset signals (resetn0
and resetn1) and a synchronous high-active enable control (en). The counting sequence is
0→2→4→6→0... or 1→3→5→7→1.... When resetn0 is low and resetn1 is high,
reset to state 0; when the resetn0 is high and resetn1 is low, reset to state 1. Output z is
same as the state. Hint: You may use Q<=Q+2 as the state transition equation because
6+2=0 and 7+2=1 for 3-bit additions.
(a) (10 pts) Write the pseudo-code for the problem
(b) (20 pts) Complete the Verilog design
module mycounter01 (clock, resetn0, resetn1, en, z);

Added by Alejandro B.

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