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Practice SRAM Arrays Consider the memory array shown below. Assume that each SRAM's address is connected to ADR[14..0] and that its R/W signal is directly connected to the array R/W input. The SRAMs' chip select inputs are driven from the array inputs as shown below. $CS0 = \overline{ADR[16]} \cdot ADR[15] \cdot CS$ $CS1 = ADR[16] \cdot \overline{ADR[15]} \cdot CS$ $CS2 = ADR[16] \cdot ADR[15] \cdot CS$ $CS3 = \overline{ADR[16]} \cdot \overline{ADR[15]} \cdot CS$ If the array is signalled to perform a read at address 09ABC$_{16}$, which SRAM device(s) will be enabled? SRAM 0 SRAM 1 SRAM 2 SRAM 3 Attempt #1: 0/1 (Score: 0/1) Allowed attempts: 1 The size (i.e., depth x width) of the memory array shown above is 1 128 k x 2 8 b. Attempt #1: 1/1 (Score: 1/1) Allowed attempts: 2 Retry penalty: 30%

Name: practice sram arrays consider the memory array shown below assume that each srams address is connected to adr140 and that its rw signal is directly connected to the array rw input the srams 06962
Uploaded: 2023-09-14T06:52:12-08:00
Duration: 1 min 53 s
Channel: Adi S
Description: practice sram arrays consider the memory array shown below assume that each srams address is connected to adr140 and that its rw signal is directly connected to the array rw input the srams 06962

          Practice SRAM Arrays
Consider the memory array shown below.
Assume that each SRAM's address is connected to ADR[14..0] and that its R/W signal is directly connected to the array R/W input. The SRAMs' chip select inputs are driven from the array inputs as shown below.
$CS0 = \overline{ADR[16]} \cdot ADR[15] \cdot CS$
$CS1 = ADR[16] \cdot \overline{ADR[15]} \cdot CS$
$CS2 = ADR[16] \cdot ADR[15] \cdot CS$
$CS3 = \overline{ADR[16]} \cdot \overline{ADR[15]} \cdot CS$
If the array is signalled to perform a read at address 09ABC$_{16}$, which SRAM device(s) will be enabled?
SRAM 0
SRAM 1
SRAM 2
SRAM 3
Attempt #1: 0/1 (Score: 0/1)
Allowed attempts: 1
The size (i.e., depth x width) of the memory array shown above is 1 128 k x 2 8 b.
Attempt #1: 1/1 (Score: 1/1)
Allowed attempts: 2 Retry penalty: 30%

practice sram arrays consider the memory array shown below assume that each srams address is connected to adr140 and that its rw signal is directly connected to the array rw input the srams 06962

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