Q: Use Pspice schematic to design a 130nm
CMOS Inverter with the following parameters:
* Gain factor Kn=400 ,
Kp=100.
* Threshold voltage Vt0n= 0.3
, Vt0p= -0.3
* Channel length modulation: NMOS=0.08 ,
PMOS=0.04
* Gate oxide capacitance Cox =
14.
* Level = 1.3 v.
* Vout= 1.3 V.
* Vin= 0.65 v.
A) Plot the Pspice simulation circuit.
B) Plot DC simulation result.
C) Plot Transient Simulation.