We assume that all memories are initialized by 0 and the branch result is known in an ID state. In addition, let us assume that all memory accesses are cache hit. Instruction Sequence strcpy: subi $sp,$sp,4 sw $s0,0($sp) addi $s0,$s0,2 L1: add $t1,$a1,$s0 lb $t2,0($t1) add $t3,$a0,$s0 sb $t2,0($t3) addi $s0,$s0,-1 bne $t2,$zero,L1 lw $s0,0($sp) add1 $sp,$sp,4 jr $ra Register number $s0 $t1 $t2 $t3 $sp $a0 $a1 Contents 0 0 0 0 3000 2000 1000 2.1 Identify all data hazards in the following sequence of instructions, when executed on the 5-stage pipelined MIPS implementation without forwarding (5 points). 2.2 Identify all data hazards in the following sequence of instructions, when executed on the 5-stage pipelined MIPS implementation with forwarding (5 points). 2.3 What is the number of cycles when the above code is executing on the 5-stage pipelined MIPS implementation without forwarding and no branch prediction (5 points)? You need to show how to get the number of cycles. 2.4 What is the number of cycles when the above code is executing on the 5-stage pipelined MIPS implementation with forwarding and always taken branch prediction (5 points)? You need to show how to get the number of cycles.