Which of the following is a Load Instruction data path? 4 Instruction [25-0] Shift Jump address [31-0] left 2 26 28 PC + 4 [31-28] Add Instruction [31-26] 0 MUX MUX ALU Add result 1 0 RegDst Jump Shift left 2 Branch MemRead MemtoReg Control ALUOP MemWrite ALUSrc RegWrite Instruction [25-21] Read PC Read address register 1 Read Instruction [20-16] data 1 Read Instruction register 2 [31-0] Instruction memory Instruction [15-11] OMUXI Write Read register data 2 Write OMUx1 Zero ALU ALU result Read Address data 1 MUXO data Registers Write Data data memory Instruction [15-0] 16 32 Sign- extend ALU control Instruction [5-01
Added by Daniela E.
Close
Step 1
Step 1: The Load instruction is a type of instruction that loads data from memory into a register. Show more…
Show all steps
Your feedback will help us improve your experience
Akash M and 98 other AP CS educators are ready to help you.
Ask a new question
Labs
Want to see this concept in action?
Explore this concept interactively to see how it behaves as you change inputs.
Key Concepts
Recommended Videos
8.3 An Acc-ISA CPU executes the following instructions using 4-bit op-codes and 4-bit address or 2’s complement data. Do the following: LD address //Acc ← Memory [address], read from LM2 LD data //Acc ← data (a 2’s complement number, sign extended) ADD data //Acc ← Acc + data (data is a 2’s complement number, sign extended) SUB data //Acc ← Acc - data (data is a 2’s complement number, sign extended) ADD (address) //Acc ← Acc + Memory[address] STM (address) //M[address] ← Acc SUB (address) //Acc ← Acc - Memory[address] JMP address //PP ← address JZ address // PP ← address (if result of the operation was zero) a) Draw a data path for the CPU assuming the DM has separate input and output bus as in the data path shown in Fig. 8.7. Do not include additional data paths not used by the instruction
Akash M.
CPU Datapath: The following figure shows the overall datapath of the simple 5-stage CPU: There are four multiplexers (MUX) in the figure, which are labeled and numbered. Please answer the following questions regarding these multiplexers. 1. Please give the two inputs of each multiplexer. (a) MUX1: i. input 1: ii. input 2: (b) MUX2: i. input 1: ii. input 2: (c) MUX3: i. input 1: ii. input 2: (d) MUX4: i. input 1: ii. input 2: 2. Given a memory load instruction, mov R0; [R1+1000]," please give the input that should be selected at each multiplexer. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 3. Given a memory store instruction, mov [R1+1000]; R0," please give the input that should be selected at each multiplexer. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 4. Given a bitwise XOR instruction, xor R0; R1; R2," please give the input that should be selected at each multiplexer. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 5. Given a conditional branch instruction, jnz 100," please give the input that should be selected at each multiplexer. Assume the branch is not taken. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 6. Given an unconditional branch instruction, jmp 100," please give the input that should be selected at each multiplexer. Unconditional branches are always taken. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4:
In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to the clock cycle in which the processor fetches the following instruction word: 1000110010100110000000000011000. Assume that the data memory is all zeros and that the processor registers have the following values at the beginning of the cycle in which the above instruction word is fetched: a. What are the outputs of the sign-extend and the jump Shift-Left-2 (near the top of Figure 4.24) for this instruction word? (2 points) b. What are the values of ALU control unit's inputs (ALUOp and Instruction operation) for this instruction? (2 points) c. For the ALU and the two add units, what are their data input values? (2 points) d. What are the values of all inputs for the "Registers" unit? (2 points)
Sri K.
Recommended Textbooks
Computer Science and Information Technology
Introduction to Programming Using Python
Computer Science - An Overview
Transcript
Watch the video solution with this free unlock.
EMAIL
PASSWORD