Question

3. [2 Grades] Write a Verilog module to implement the circuit outlined by the circuit shown in the Figure 6. The circuit has one input (which is connected to be one of the sliding switches). If the input is low, letter "L" is shown on the 7-segment display. Otherwise, the letter "H" is shown. a a a a ?b b 7-segment decoder b f b C d g ?e 7-segment decoder ?C ?d ?e f e C f ?g e C g d Figure 6. The toggle switch controls the letter displayed on the seven-segment display c. [2 Grades] Upgrade your implementation in experiment step 4(a) (4-RCA Adder) to add 20 bits instead of 4 using generate blocks and develop a self-checking testbench to test your module and simulate it d. [2 Grades] Upgrade the implementation in the previous question to realize a 20-RCA Adder/Subtractor using if statements

          3. [2 Grades] Write a Verilog module to implement the circuit outlined by the circuit shown in the
Figure 6. The circuit has one input (which is connected to be one of the sliding switches). If the
input is low, letter "L" is shown on the 7-segment display. Otherwise, the letter "H" is shown.
a
a
a
a
?b
b
7-segment
decoder
b
f
b
C
d
g
?e
7-segment
decoder
?C
?d
?e
f
e
C
f
?g
e
C
g
d
Figure 6. The toggle switch controls the letter displayed on the seven-segment display
c. [2 Grades] Upgrade your implementation in experiment step 4(a) (4-RCA Adder) to add 20 bits
instead of 4 using generate blocks and develop a self-checking testbench to test your module and
simulate it
d. [2 Grades] Upgrade the implementation in the previous question to realize a 20-RCA
Adder/Subtractor using if statements

3. [2 Grades] Write a Verilog module to implement the circuit outlined by the circuit shown in the
Figure 6. The circuit has one input (which is connected to be one of the sliding switches). If the
input is low, letter "L" is shown on the 7-segment display. Otherwise, the letter "H" is shown.
a
a
a
a
?b
b
7-segment
decoder
b
f
b
C
d
g
?e
7-segment
decoder
?C
?d
?e
f
e
C
f
?g
e
C
g
d
Figure 6. The toggle switch controls the letter displayed on the seven-segment display
c. [2 Grades] Upgrade your implementation in experiment step 4(a) (4-RCA Adder) to add 20 bits
instead of 4 using generate blocks and develop a self-checking testbench to test your module and
simulate it
d. [2 Grades] Upgrade the implementation in the previous question to realize a 20-RCA
Adder/Subtractor using if statements

Added by Caitlin E.

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