Goals: • To learn general-purpose register architectures. • To learn encoding an instruction set. Questions: 100 points: (1) 30 points, (2) 70 points 1. [30 points] The design of MIPS provides for 32 general-purpose registers and 32 floating-point registers. If registers are good, are more registers better? List and discuss as many trade-offs as you can that should be considered by instruction set architecture designers examining whether to, and how much to, increase the numbers of MIPS registers. 2. [70 points] Consider the case of a processor with an instruction length of 12 bits and with 32 general purpose registers so the size of the address fields is 5 bits. 2.1 [35points] Is it possible to have instruction encodings for the following? You must provide encoding details to explain your answers. • 3 two-address instructions • 30 one-address instructions • 45 zero address instructions 2.2 [35points] Is it possible to have instruction encodings for the following? You must provide encoding details to explain your answers. • 3 two-address instructions • 31 one-address instructions • 35 zero address instructions HINTS: 1. In 2.1 and 2.2, are we allowed to assume that all of the bits not used for the register addresses can be dedicated to the opcode? For example, is it accurate to say that a zero address instruction has a 12-bit opcode, allowing for 2^12 different instruction encodings (2^7 for one address instructions, etc)? Answer: Yes. all bits not used for register names are dedicated to opcode.
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[30 points] The design of MIPS provides for 32 general-purpose registers and 32 floating-point registers. If registers are good, are more registers better? List and discuss as many trade-offs as you can that should be considered by instruction set architecture Show more…
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A hypothetical ISA supports 6 different operations. How many bits of the instruction must be allocated for the opcode field? 1. The operands must also be encoded into the instruction. The most common type of operand is a value contained in a register in the processor's register file. Since the value is in a register, we just need to encode enough information to identify which register. The hypothetical ISA from the previous question states that the register file contains 32 registers. How many bits must be allocated to identify each register operand? 2. The hypothetical ISA from the previous questions on this page includes an ADD instruction that performs the operation Rd. Note that the arrow (←) used in the above notation points to where the result of the operation will be stored. When the processor executes this instruction, it will read the values from the source registers symbolized by Ra and Rb and stores their sum in the destination register symbolized by Rd. How many bits do we need to encode the ADD instruction? 3. Some instructions have different numbers of operands. The hypothetical ISA from the previous questions on this page also has a bitwise NOT instruction that performs the operation Rd, and which only requires one source register. Remember we will always assume that all instructions in a given ISA are encoded with the same number of bits. If all instructions in this ISA are as long as the ADD instruction, how many bits would be unused when encoding the NOT instruction?
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Design a multicycle MIPS processor (datapath, ALU and control unit) for the instruction set given below. Refer to the MIPS reference sheet for the detailed operation of each instruction. Mnemonic Instruction Name lui Load upper immediate slti Set less than immediate jr Jump register jal Jump and link ori OR immediate a. Provide a breakdown of each instruction into smaller steps so that each step is executed in one cycle. Also, design the ALU required by the processor. b. Provide an incremental, step-by-step, design of the datapath i.e. in the first diagram, design the datapath for the first instruction lui, then (in a new diagram) add/remove connections and functional units to accommodate the second instruction slti in the datapath, then (in a new diagram) add/remove connections and functional units to accommodate the third instruction jr in the datapath, and so on. So, your datapath should consist of 5 incremental diagrams, like what we did it in the lecture slides. Your incremental datapath design should also include the necessary control signals for multiplexers, functional units, register enables etc. c. Provide the state transition diagram for the control unit FSM of the multicycle processor. NOTE: Your design should be optimized and should only include the functional units, datapath connections and control signals that enable the execution of the instruction set given in the table above. Do not include any unnecessary units/connections/control signals that are not required by the instruction set.
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