A. Scott MUX 3 RALU MUX 1 A M3:0 0 LOAD_RO R_ALU/R1 D CE LOAD_R1 Reg R0 C CLR RST CE Reg R1 CLR RST(asyn) LOAD_OP MUX 2 0 4 MUX 2 0 4 CE A_OR1 D Reg OP(1:0) output port CLK C CLR RST M2 D CLK MI ALU ALU_OUT LOAD(ALU) LOADI (ALU) ADD(1010) ADD(1010) SUB MUX 4 MUX 5 0 R_JR IR(7:5) MS IR(3:0) A4 4. [20 pts] Express the control signals, 0/1/d (for M1-M5, and register Loads) required to facilitate the assembly commands as shown in the following table. [0.5 pts/ea.] M1 M2 M3 M4 M5 LOAD_R0 LOAD_R1 LO Command IN R0 ADDI R0,10 MOV R1,R0 SRO R0,R1 OUT R0 (*Recall that data to the SRO command enters the ALU through the R_IR signal)
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For the given Single Cycle Processor, Add functionality for the given I-TYPE instructions below ANDI (ANDI rt, rs, imm) ORI (ORI rt, rs, imm) XORI (XORI rt, rs, imm) Update the Control Unit signal table below for the new instructions and modify the Datapath if required for the new instructions. For the new instructions include an explanation supporting the functionality. INSTRUCTION OP[5:0] REGWRITE REGDST ALUSRC BRANCH MEMWRITE MEMREG ALU- JUMP OP[1:0] R-TYPE 000000 1 1 0 0 0 0 10 0 SW 101011 0 X 1 0 1 X 00 0 LW 100011 1 0 1 0 0 1 00 0 BEQ 000100 0 X 0 1 0 X 01 0 J 000010 0 X X X 0 X XX 1 ANDI 001100 ORI 001101 XORI 001110
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CPU Datapath: The following figure shows the overall datapath of the simple 5-stage CPU: There are four multiplexers (MUX) in the figure, which are labeled and numbered. Please answer the following questions regarding these multiplexers. 1. Please give the two inputs of each multiplexer. (a) MUX1: i. input 1: ii. input 2: (b) MUX2: i. input 1: ii. input 2: (c) MUX3: i. input 1: ii. input 2: (d) MUX4: i. input 1: ii. input 2: 2. Given a memory load instruction, mov R0; [R1+1000]," please give the input that should be selected at each multiplexer. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 3. Given a memory store instruction, mov [R1+1000]; R0," please give the input that should be selected at each multiplexer. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 4. Given a bitwise XOR instruction, xor R0; R1; R2," please give the input that should be selected at each multiplexer. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 5. Given a conditional branch instruction, jnz 100," please give the input that should be selected at each multiplexer. Assume the branch is not taken. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 6. Given an unconditional branch instruction, jmp 100," please give the input that should be selected at each multiplexer. Unconditional branches are always taken. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4:
Problem 1. Understanding the Multiplexer (5 points) Below on the left is the logic symbol for a 4:1 Multiplexer (MUX). You can copy this symbol to make logic diagram later in the post-lab report. On the right is the 4:1 MUX IC Pinout (same diagram is on second page of ic_diagrams.pdf). DO D1 D2 D3 Y S1 S0 1G 1 16 VDD S1 2 15 2G 1D3 3 14 S0 1D2 4 13 2D3 1D1 5 12 2D2 1D0 6 11 2D1 1Y 7 10 2D0 GND 8 9 2Y Two 4:1 Multiplexers D3:0: data S1:0: select Y: output Gb: enable 74153 4:1 Mux Multiplexer Symbol for Logic Diagram IC Pinout Legend for IC Pinout 1.1 How many select bits are used for the 4:1 Mux? 1.2 Which select bit is the most significant bit? 1.3 Suppose S1 = 1, S0 = 0 and 1G = 0, then which signal will be assigned to output 1Y? 1.4 Now we still have S1 = 1, S0 = 0 but 1G = 1, then what will 1Y be? 1.5 Notice that we also have another set of inputs 2D and output 2Y. Explain how 2Y is related to 2D in one or two sentences.
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